XC5VLX50T-1FFG1136CES Xilinx Inc, XC5VLX50T-1FFG1136CES Datasheet - Page 318
![IC FPGA VIRTEX-5 ES 50K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50T-1FFG1136CES
Manufacturer Part Number
XC5VLX50T-1FFG1136CES
Description
IC FPGA VIRTEX-5 ES 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-1FFG1136CES
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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XC5VLX50T-1FFG1136CES
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Chapter 7: SelectIO Logic Resources
ILOGIC Resources
318
The ILOGIC block shown in
X-Ref Target - Figure 7-1
ILOGIC can support the following operations:
•
•
•
•
All ILOGIC block registers have a common clock enable signal (CE1) that is active High by
default. If left unconnected, the clock enable pin for any storage element defaults to the
active state.
All ILOGIC block registers have a common synchronous or asynchronous set and reset (SR
and REV signals). The set/reset input pin, SR forces the storage element into the state
specified by the SRVAL attributes. When using SR, a second input, REV forces the storage
element into the opposite state. The reset condition predominates over the set condition.
Table 7-1
Table 7-1: Truth Table when SRVAL = 0 (Default Condition)
SR
Edge-triggered D-type flip-flop
IDDR mode (OPPOSITE_EDGE or SAME_EDGE or SAME_EDGE_PIPELINED). See
Input DDR Overview (IDDR), page 319
Level sensitive latch
Asynchronous/combinatorial
0
0
1
1
and
DDLY
CE1
CLK
REV
SR
D
REV
Table 7-2
0
1
0
1
NOP
Reset
Set
Reset
describe the operation of SR in conjunction with REV.
www.xilinx.com
Figure 7-1: ILOGIC Block Diagram
Figure
7-1.
Function
for further discussion on input DDR.
D
CE
CK
SR
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
REV
Q1
Q2
ug190_7_01_050906
Q1
Q2
O
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