XC5VLX50T-1FFG1136CES Xilinx Inc, XC5VLX50T-1FFG1136CES Datasheet - Page 180
![IC FPGA VIRTEX-5 ES 50K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50T-1FFG1136CES
Manufacturer Part Number
XC5VLX50T-1FFG1136CES
Description
IC FPGA VIRTEX-5 ES 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-1FFG1136CES
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Company:
Part Number:
XC5VLX50T-1FFG1136CES
Manufacturer:
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Quantity:
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Chapter 5: Configurable Logic Blocks (CLBs)
180
Distributed RAM and Memory (Available in SLICEM only)
The initial state after configuration or global initial state is defined by separate INIT0 and
INIT1 attributes. By default, setting the SRLOW attribute sets INIT0, and setting the
SRHIGH attribute sets INIT1. Virtex-5 devices can set INIT0 and INIT1 independent of
SRHIGH and SRLOW.
The configuration options for the set and reset functionality of a register or a latch are as
follows:
•
•
•
•
•
•
•
Multiple LUTs in a SLICEM can be combined in various ways to store larger amount of
data.
The function generators (LUTs) in SLICEMs can be implemented as a synchronous RAM
resource called a distributed RAM element. RAM elements are configurable within a
SLICEM to implement the following:
•
•
•
•
•
•
•
•
•
•
•
Distributed RAM modules are synchronous (write) resources. A synchronous read can be
implemented with a storage element or a flip-flop in the same slice. By placing this flip-
flop, the distributed RAM performance is improved by decreasing the delay into the clock-
to-out value of the flip-flop. However, an additional clock latency is added. The distributed
elements share the same clock input. For a write operation, the Write Enable (WE) input,
driven by either the CE or WE pin of a SLICEM, must be set High.
No set or reset
Synchronous set
Synchronous reset
Synchronous set and reset
Asynchronous set (preset)
Asynchronous reset (clear)
Asynchronous set and reset (preset and clear)
Single-Port 32 x 1-bit RAM
Dual-Port 32 x 1-bit RAM
Quad-Port 32 x 2-bit RAM
Simple Dual-Port 32 x 6-bit RAM
Single-Port 64 x 1-bit RAM
Dual-Port 64 x 1-bit RAM
Quad-Port 64 x 1-bit RAM
Simple Dual-Port 64 x 3-bit RAM
Single-Port 128 x 1-bit RAM
Dual-Port 128 x 1-bit RAM
Single-Port 256 x 1-bit RAM
www.xilinx.com
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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