XC5VLX50T-1FFG1136CES Xilinx Inc, XC5VLX50T-1FFG1136CES Datasheet - Page 87
![IC FPGA VIRTEX-5 ES 50K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50T-1FFG1136CES
Manufacturer Part Number
XC5VLX50T-1FFG1136CES
Description
IC FPGA VIRTEX-5 ES 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-1FFG1136CES
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
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Quantity
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Company:
Part Number:
XC5VLX50T-1FFG1136CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
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- Download datasheet (14Mb)
X-Ref Target - Figure 2-20
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
PSDONE
CLKFB
CLKFX
PSCLK
CLKIN
DO(0)
DO(1)
DO(2)
PSEN
DO(3)
Status Flags
The example in
shift overflow and CLKIN/CLKFB/CLKFX failure.
•
•
•
•
Clock Event 1
Prior to the beginning of this timing diagram, CLK0 (not shown) is already phase-
shifted at its maximum value. At clock event 1, PSDONE is asserted. However, since
the DCM has reached its maximum phase-shift capability no phase adjustment is
performed. Instead, the phase-shift overflow status pin DO(0) is asserted to indicate
this condition.
Clock Event 2
The CLKFX output stops toggling. Within 257 to 260 clock cycles after this event, the
CLKFX stopped status DO(2) is asserted to indicate that the CLKFX output stops
toggling.
Clock Event 3
The CLKFB input stops toggling. Within 257 to 260 clock cycles after this event, the
CLKFB stopped status DO(3) is asserted to indicate that the CLKFB output stops
toggling.
Clock Event 4
The CLKIN input stops toggling. Within 9 clock cycles after this event, DO(1) is
asserted to indicate that the CLKIN output stops toggling.
1
2
Figure 2-20: Status Flags Example
Figure 2-20
www.xilinx.com
shows the behavior of the status flags in the event of a phase-
3
257 - 260 Cycles
4
DCM Timing Models
ug190_2_21_042406
87
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