XC5VLX50T-1FFG1136CES Xilinx Inc, XC5VLX50T-1FFG1136CES Datasheet - Page 257
![IC FPGA VIRTEX-5 ES 50K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50T-1FFG1136CES
Manufacturer Part Number
XC5VLX50T-1FFG1136CES
Description
IC FPGA VIRTEX-5 ES 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-1FFG1136CES
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50T-1FFG1136CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
- Current page: 257 of 385
- Download datasheet (14Mb)
X-Ref Target - Figure 6-46
X-Ref Target - Figure 6-47
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
External Termination
DIFF_HSTL_II
DIFF_HSTL_II
DIFF_HSTL_II
DIFF_HSTL_II_DCI
DIFF_HSTL_II_DCI
DCI
+
–
Figure 6-46: Differential HSTL (1.5V) Class II DCI Unidirectional Termination
Figure 6-47: Differential HSTL (1.5V) Class II Bidirectional Termination
V
V
CCO
CCO
IOB
Figure 6-46
differential HSTL Class II (1.5V) with unidirectional DCI termination.
Figure 6-47
differential HSTL Class II (1.5V) with bidirectional termination.
= 1.5V
= 1.5V
2R
2R
2R
2R
IOB
VRP
VRN
VRP
VRN
V
V
TT
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
TT
= 0.75V
shows a sample circuit illustrating a valid termination technique for
shows a sample circuit illustrating a valid termination technique for
= 0.75V
50Ω
50Ω
www.xilinx.com
Z 0
Z 0
Z 0
Z 0
Specific Guidelines for I/O Supported Standards
IOB
V
V
CCO
CCO
2R
2R
2R
2R
= 1.5V
= 1.5V
V
V
VRP
VRN
VRP
VRN
TT
50Ω
TT
50Ω
= 0.75V
= 0.75V
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
IOB
DIFF_HSTL_II_DCI
DIFF_HSTL_II
DIFF_HSTL_II
DIFF_HSTL_II
+
–
–
+
ug190_6_44_020306
ug190_6_45_020306
257
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