XC5VLX50T-1FFG1136CES Xilinx Inc, XC5VLX50T-1FFG1136CES Datasheet - Page 53
![IC FPGA VIRTEX-5 ES 50K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50T-1FFG1136CES
Manufacturer Part Number
XC5VLX50T-1FFG1136CES
Description
IC FPGA VIRTEX-5 ES 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-1FFG1136CES
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
XC5VLX50T-1FFG1136CES
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DCM Control and Data Input Ports
Dynamic Reconfiguration Clock Input - DCLK
Reset Input - RST
Phase-Shift Increment/Decrement Input - PSINCDEC
The dynamic reconfiguration clock (DCLK) input pin provides the source clock for the
DCM's dynamic reconfiguration circuit. The frequency of DCLK can be asynchronous (in
phase and frequency) to CLKIN. The dynamic reconfiguration clock signal is driven by
any clock source (external or internal), including:
1.
2.
3.
4.
The frequency range of DCLK is described in the Virtex-5 FPGA Data Sheet. When dynamic
reconfiguration is not used, this input must be tied to ground. See the dynamic
reconfiguration chapter in the Virtex-5 FPGA Configuration Guide for more information.
The reset (RST) input pin resets the DCM circuitry. The RST signal is an active High
asynchronous reset. Asserting the RST signal asynchronously forces all DCM outputs Low
(the LOCKED signal, all status signals, and all output clocks) after some propagation delay.
When the reset is asserted, the last cycle of the clocks can exhibit a short pulse and a
severely distorted duty cycle, or no longer be deskewed with respect to one another while
asserting High. Deasserting the RST signal starts the locking process at the next CLKIN
cycle.
To ensure a proper DCM reset and locking process, the RST signal must be held until the
CLKIN signal is present and stable for at least three CLKIN cycles.
The time it takes for the DCM to lock after a reset is specified in the Virtex-5 FPGA Data
Sheet as LOCK_DLL (for a DLL output) and LOCK_FX (for a DFS output). These are the
CLK and CLKFX outputs described in
higher frequencies. The worse-case numbers are specified in the Virtex-5 FPGA Data Sheet.
In all designs, the DCM must be held in reset until CLKIN is stable.
The phase-shift increment/decrement (PSINCDEC) input signal must be synchronous
with PSCLK. The PSINCDEC input signal is used to increment or decrement the phase-
shift factor when PSEN is activated. As a result, the output clocks are shifted. The
PSINCDEC signal is asserted High for increment or deasserted Low for decrement. This
input must be tied to ground when the CLKOUT_PHASE_SHIFT attribute is set to NONE
or FIXED.
IBUF – Input Buffer
IBUFG – Global Clock Input Buffer
Only the IBUFGs on the same half of the device (top or bottom) as the DCM can be
used to drive a CLKIN input of the DCM.
BUFGCTRL – An Internal Global Buffer
Internal Clock – Any internal clock using general purpose routing.
www.xilinx.com
DCM Clock Output
Ports. The DCM locks faster at
DCM Ports
53
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