XC5VLX50T-1FFG1136CES Xilinx Inc, XC5VLX50T-1FFG1136CES Datasheet - Page 262
![IC FPGA VIRTEX-5 ES 50K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50T-1FFG1136CES
Manufacturer Part Number
XC5VLX50T-1FFG1136CES
Description
IC FPGA VIRTEX-5 ES 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-1FFG1136CES
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50T-1FFG1136CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
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Chapter 6: SelectIO Resources
X-Ref Target - Figure 6-52
262
DCI
HSTL_II_T_DCI (1.5V) Split-Thevenin Termination
HSTL_II_T_DCI
Figure 6-52: HSTL_II_T_DCI (1.5V) Split-Thevenin Termination
Table 6-20
Table 6-20: HSTL Class IV DC Voltage Specifications
Figure 6-52
HSTL_II_T_DCI (1.5V) with on-chip split-Thevenin termination. In this bidirectional case,
when 3-stated, the termination is invoked on the receiver and not on the driver.
Notes:
1. V
2. Per EIA/JESD8-6, “The value of V
V
V
V
V
V
V
V
I
I
OH
OL
Not 3-stated
CCO
REF
TT
IH
IL
OH
OL
the use conditions specified by the user.”
V
OL
at V
REF
at V
(2)
and V
= 0.75V
OL
OH
lists the HSTL Class IV DC voltage specifications.
(mA)
shows a sample circuit illustrating a valid termination technique for
IOB
OH
(mA)
for lower drive currents are sample tested.
(1)
(1)
Z 0
www.xilinx.com
REF
is to be selected by the user to provide optimum noise margin in
3-stated
IOB
V
CCO
2R
2R
= 1.5V
VRP
VRN
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
V
V
V
REF
CCO
REF
Min
1.40
–8
48
= 0.75V
–
–
–
–
+ 0.1
– 0.4
HSTL_II_T_DCI
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
V
Typ
1.50
0.90
+
–
CCO
–
–
–
–
–
–
ug190_6_90_041206
V
REF
Max
1.60
0.4
–
–
–
–
–
–
– 0.1
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