ADE7166ASTZF8 Analog Devices Inc, ADE7166ASTZF8 Datasheet - Page 130

• Manufacturer Part Number: ADE7166ASTZF8
• Description: IC ENERGY METER 1PHASE 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7166ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE71xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7566/ADE7569/ADE7166/ADE7169
Table 141. SPI Configuration SFR 2 (SPIMOD2, 0xE9)
Bit
7
6
5
4
3
2
1
0
Mnemonic
SPIODO
SPIMS_b
SPICPOL
SPILSBF
SPICONT
SPIEN
SPICPHA
TIMODE
Default
0
0
0
0
0
0
0
1
Description
Master Mode, SPI Continuous Transfer Mode Enable Bit.
SPICONT
0
1
SPI Interface Enable Bit.
SPIEN
0
1
SPI Open-Drain Output Configuration Bit.
SPIODO
0
1
SPI Master Mode Enable Bit.
SPIMS_b
0
1
SPI Clock Polarity Configuration Bit (see Figure 110).
SPICPOL
0
1
SPI Clock Phase Configuration Bit (see Figure 110).
SPICPHA
0
1
Master Mode, LSB First Configuration Bit.
SPILSBF
0
1
Transfer and Interrupt Mode of the SPI Interface.
TIMODE
1
Result
The SPI interface stops after one byte is transferred and SS is deasserted. A new data transfer can
be initiated after a stalled period.
The SPI interface continues to transfer data until no valid data is available in the SPI2CTx SFR. SS
remains asserted until the SPI2CTx SFR and the transmit shift registers are empty.
Result
The SPI interface is disabled.
The SPI interface is enabled.
Result
Internal pull-up resistors are connected to the SPI outputs.
The SPI outputs are open drain and need external pull-up resistors. The pull-up voltage should
not exceed the specified operating voltage.
Result
The SPI interface is defined as a slave.
The SPI interface is defined as a master.
Result
The default state of SCLK is low, and the first SCLK edge is rising. Depending on the SPICPHA bit,
the SPI data output changes state on the falling or rising edge of SCLK while the SPI data input is
sampled on the rising or falling edge of SCLK.
The default state of SCLK is high, and the first SCLK edge is falling. Depending on the SPICPHA
bit, the SPI data output changes state on the rising or falling edge of SCLK while the SPI data
input is sampled on the falling or rising edge of SCLK.
Result
The SPI data output changes state when SS goes low at the second edge of SCLK and then every
two subsequent edges, whereas the SPI data input is sampled at the first SCLK edge and then
every two subsequent edges.
The SPI data output changes state at the first edge of SCLK and then every two subsequent
edges, whereas the SPI data input is sampled at the second SCLK edge and then every two
subsequent edges.
Result
The MSB of the SPI outputs is transmitted first.
The LSB of the SPI outputs is transmitted first.
Result
This bit must be left set for proper operation.
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