ADE7166ASTZF8 Analog Devices Inc, ADE7166ASTZF8 Datasheet - Page 86

• Manufacturer Part Number: ADE7166ASTZF8
• Description: IC ENERGY METER 1PHASE 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7166ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE71xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7566/ADE7569/ADE7166/ADE7169
Mnemonic
MISCELLANEOUS
READ-MODIFY-WRITE INSTRUCTIONS
Some 8052 instructions read the latch and others read the pin.
The state of the pin is read for instructions that input a port bit.
Instructions that read the latch rather than the pins are the ones
that read a value, possibly change it, and rewrite it to the latch.
Because these instructions involve modifying the port, it is
assumed that the pins being modified are outputs, so the output
state of the pin is read from the latch. This prevents a possible
misinterpretation of the voltage level of a pin. For example, if a
port pin is used to drive the base of a transistor, a 1 is written to
the bit to turn on the transistor. If the CPU reads the same port
bit at the pin rather than the latch, it reads the base voltage of
the transistor and interprets it as Logic 0. Reading the latch
rather than the pin returns the correct value of 1.
The instructions that read the latch rather than the pins are
called read-modify-write instructions and are listed in Table 65.
When the destination operand is a port or a port bit, these
instructions read the latch rather than the pin.
Table 65. Read-Modify-Write Instructions
Instruction
ANL
ORL
XRL
JBC
CPL
INC
DEC
DJNZ
MOV PX.Y,C
CLR PX.Y
SETB PX.Y
1
These instructions read the port byte (all 8 bits), modify the addressed bit,
and write the new byte back to the latch.
JNC rel
JZ rel
JNZ rel
DJNZ Rn,rel
LJMP
LCALL addr16
JB bit,rel
JNB bit,rel
JBC bit,rel
CJNE A,dir,rel
CJNE A,#data,rel
CJNE Rn,#data,rel
CJNE @Ri,#data,rel
DJNZ dir,rel
NOP
1
1
1
ANL P0,A
ORL P1,A
XRL P2,A
CPL P2.0
INC P2
DEC P2
DJNZ P0,LABEL
MOV P0.0,C
CLR P0.0
SETB P0.0
Example
JBC P1.1,LABEL
Logical AND.
Logical OR.
Logical EX-OR.
Increment.
Decrement.
Description
Jump if Bit = 1 and Clear Bit.
Complement Bit.
Decrement and Jump if Not Zero.
Move Carry to Bit Y of Port X.
Clear Bit Y of Port X.
Set Bit Y of Port X.
Description
Jump on Carry Equal to 0.
Jump on Accumulator = 0.
Jump on Accumulator Not Equal to 0.
Decrement Register, JNZ Relative.
Long Jump Unconditional.
Long Jump to Subroutine.
Jump on Direct Bit = 1.
Jump on Direct Bit = 0.
Jump on Direct Bit = 1 and Clear.
Compare A, Direct JNE Relative.
Compare A, Immediate JNE Relative.
Compare Register, Immediate JNE Relative.
Compare Indirect, Immediate JNE Relative.
Decrement Direct Byte, JNZ Relative.
No Operation.
Rev. A | Page 86 of 144
INSTRUCTIONS THAT AFFECT FLAGS
Many instructions explicitly modify the carry bit, such as the
MOV C bit and CLR C instructions. Other instructions that
affect status flags are listed in this section.
ADD A, Source
This instruction adds the source to the accumulator. No status
flags are referenced by the instruction.
Affected Status Flags
C
OV
AC
ADDC A, Source
This instruction adds the source and the carry bit to the accu-
mulator. The carry status flag is referenced by the instruction.
Affected Status Flags
C
OV
AC
Set if there is a carry out of Bit 7. Cleared otherwise.
Used to indicate an overflow if the operands are
unsigned.
Set if there is a carry out of Bit 6 or a carry out of
Bit 7, but not if both are set. Used to indicate an
overflow for signed addition. This flag is set if two
positive operands yield a negative result or if two
negative operands yield a positive result.
Set if there is a carry out of Bit 3. Cleared otherwise.
Set if there is a carry out of Bit 7. Cleared otherwise.
Used to indicate an overflow if the operands are
unsigned.
Set if there is a carry out of Bit 6 or a carry out of Bit 7,
but not if both are set. Used to indicate an overflow
for signed addition. This flag is set if two positive
operands yield a negative result or if two negative
operands yield a positive result.
Set if there is a carry out of Bit 3. Cleared otherwise.
Bytes
2
2
2
2
3
3
3
3
3
3
3
3
3
3
1
Cycles
3
3
3
3
4
4
4
4
4
4
4
4
4
4
1