ADE7166ASTZF8 Analog Devices Inc, ADE7166ASTZF8 Datasheet - Page 54

• Manufacturer Part Number: ADE7166ASTZF8
• Description: IC ENERGY METER 1PHASE 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7166ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE71xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7566/ADE7569/ADE7166/ADE7169
Line Voltage SAG Detection
In addition to detection of the loss of the line voltage signal
(zero crossing), the ADE7566/ADE7569/ADE7166/ADE7169
can also be programmed to detect when the absolute value of
the line voltage drops below a certain peak value for a number
of line cycles. This condition is illustrated in Figure 56.
Figure 56 shows the line voltage falling below a threshold that is
set in the SAG level register (SAGLVL[15:0]) for three line
cycles. The quantities 0 and 1 are not valid for the SAGCYC
register, and the contents represent one more than the desired
number of full line cycles. For example, when the SAG cycle
(SAGCYC[7:0]) contains 0x04, FSAG in the Power Management
Interrupt Flag SFR (IPSMF, 0xF8) is set at the end of the third
line cycle after the line voltage falls below the threshold. If the SAG
enable bit (ESAG) in the Power Management Interrupt Enable SFR
(IPSME, 0xEC) is set, the 8052 core has a pending power supply
monitoring interrupt. The PSM interrupt stays active until the
ESAG bit is cleared (see the
(PSM) section).
In
after the signal on the voltage channel first dropped below the
threshold level.
SAG Level Set
The 2-byte contents of the SAG level register (SAGLVL, 0x14)
are compared to the absolute value of the output from LPF1.
Therefore, when LPF1 is enabled, writing 0x2038 to the SAG
level register puts the SAG detection level at full scale (see
Figure 56). Writing 0x00 or 0x01 puts the SAG detection level at
0. The SAG level register is compared to the input of the ZX
detection, and detection is made when the contents of the SAG
level register are greater.
Peak Detection
The ADE7566/ADE7569/ADE7166/ADE7169 can also be
programmed to detect when the absolute value of the voltage or
current channel exceeds a specified peak value. Figure 57
illustrates the behavior of the peak detection for the voltage
channel. Both voltage and current channels are monitored at the
same time.
SAGLVL [15:0]
FULL SCALE
Figure 56
SAG FLAG
, the SAG flag (FSAG) is set on the fifth line cycle
SAGCYC [7:0] = 0x04
3 LINE CYCLES
Figure 56. SAG Detection
VOLTAGE CHANNEL
Power Supply Monitor Interrupt
SAG RESET LOW
WHEN VOLTAGE
CHANNEL EXCEEDS
SAGLVL [15:0] AND
SAG FLAG RESET
Rev. A | Page 54 of 144
Figure 57 shows a line voltage exceeding a threshold that is set
in the voltage peak register (VPKLVL[15:0]). The voltage peak
event is recorded by setting the PKV flag in the Interrupt Status
3 SFR (MIRQSTH, 0xDE). If the PKV enable bit is set in the
Interrupt Enable 3 SFR (MIRQENH, 0xDB), the 8052 core has a
pending ADE interrupt. Similarly, the current peak event is
recorded by setting the PKI flag in Interrupt Status 3 SFR
(MIRQSTH, 0xDE). The ADE interrupt stays active until the
PKV or PKI status bit is cleared (see the
Interrupts section).
Peak Level Set
The contents of the VPKLVL and IPKLVL registers are compared
to the absolute value of the voltage and current channels 2 MSBs,
respectively. Thus, for example, the nominal maximum code
from the current channel ADC with a full-scale signal is
0x28F5C2 (see the Current Channel ADC section). Therefore,
writing 0x28F5 to the IPKLVL register puts the current channel,
peak detection level at full scale and sets the current peak
detection to its least sensitive value. Writing 0x00 puts the
current channel detection level at 0. The detection is done by
comparing the contents of the IPKLVL register to the incoming
current channel sample. The PKI flag indicates that the peak level is
exceeded. If the PKI or PKV bit is set in the Interrupt Enable 3
SFR (MIRQENH, 0xDB), the 8052 core has a pending ADE
interrupt.
Peak Level Record
Each ADE7566/ADE7569/ADE7166/ADE7169 records the
maximum absolute value reached by the voltage and current
channels in two different registers, IPEAK and VPEAK,
respectively. Each register is a 24-bit unsigned register that is
updated each time the absolute value of the waveform sample
from the corresponding channel is above the value stored in the
VPEAK or IPEAK register. The contents of the VPEAK register
correspond to the maximum absolute value observed on the
voltage channel input. The contents of IPEAK and VPEAK
represent the maximum absolute value observed on the current
and voltage input, respectively. Reading the RSTVPEAK and
RSTIPEAK registers clears their respective contents after the read
operation.
IN MIRQSTH SFR
PKV INTERRUPT
RESET BIT PKV
VPKLVL[15:0]
FLAG
V
2
Figure 57. Peak Level Detection
Energy Measurement
PKV RESET
LOW WHEN
MIRQSTH SFR
IS READ