ADE7166ASTZF8 Analog Devices Inc, ADE7166ASTZF8 Datasheet - Page 96

• Manufacturer Part Number: ADE7166ASTZF8
• Description: IC ENERGY METER 1PHASE 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7166ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE71xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7566/ADE7569/ADE7166/ADE7169
LCD DRIVER
Using shared pins, the LCD module is capable of directly driving an
LCD panel of 17 × 4 segments without compromising any
ADE7566/ADE7569/ADE7166/ADE7169 functions. It is
capable of driving LCDs with 2×, 3×, and 4× multiplexing. The
LCD waveform voltages generated through internal charge
pump circuitry support up to 5 V LCDs. An external resistor
ladder for LCD waveform voltage generation is also supported.
Each ADE7566/ADE7569/ADE7166/ADE7169 has an embedded
LCD control circuit, driver, and power supply circuit. The LCD
module is functional in all operating modes (see the Operating
Modes section).
Table 77. LCD Driver SFRs
SFR Address
0x95
0x96
0x97
0x9C
0xAC
0xAE
0xB1
0xED
Table 78. LCD Configuration SFR (LCDCON, 0x95)
Bit
7
6
5
4
3
2
1 to 0
Mnemonic
LCDEN
LCDRST
BLINKEN
LCDPSM2
CLKSEL
BIAS
LMUX[1:0]
Value
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
LCD Enable. If this bit is set, the LCD driver is enabled.
LCD Data Registers Reset. If this bit is set, the LCD data registers are reset to zero.
Blink Mode Enable Bit. If this bit is set, blink mode is enabled. The blink mode is configured by the
BLKMOD[1:0] and BLKFREQ[1:0] bits in the LCD Clock SFR (LCDCLK, 0x96).
Forces LCD off when in PSM2 (Sleep Mode). Note that the internal voltage reference must be enabled by setting
the REF_BAT_EN bit in the Peripheral Configuration SFR (PERIPH, 0xF4) to allow LCD operation in PSM2.
LCDPSM2
0
1
LCD Clock Selection.
CLKSEL
0
1
Bias Mode.
BIAS
0
1
LCD Multiplex Level.
LMUX[1:0]
00
01
10
11
Name
LCDCON
LCDCLK
LCDSEGE
LCDCONX
LCDPTR
LCDDAT
LCDCONY
LCDSEGE2
Result
The LCD is disabled or enabled in PSM2 by the LCDEN bit.
The LCD is disabled in PSM2 regardless of LCDEN setting.
Result
f
f
Result
1/2
1/3
Result
Reserved.
2× Multiplexing. FP27/COM3 is used as FP27. FP28/COM2 is used as FP28.
3× Mulitplexing. FP27/COM3 is used as FP27. FP28/COM2 is used as COM2.
4× Multiplexing. FP27/COM3 is used as COM3. FP28/COM2 is used as COM2.
LCDCLK
LCDCLK
= 2048 Hz
= 128 Hz
Rev. A | Page 96 of 144
Description
LCD Configuration SFR (see Table 78).
LCD Clock (see Table 82).
LCD Segment Enable (see Table 85).
LCD Configuration X (see Table 79).
LCD Pointer (see Table 86).
LCD Data (see Table 87).
LCD Configuration Y (see Table 81).
LCD Segment Enable 2 (see Table 88).
LCD REGISTERS
There are six LCD control registers that configure the driver for
the specific type of LCD in the end system and set up the user
display preferences. The LCD Configuration SFR (LCDCON,
0x95), LCD Configuration X SFR (LCDCONX, 0x9C), and
LCD Configuration Y SFR (LCDCONY, 0xB1) contain general
LCD driver configuration information including the LCD enable
and reset, as well as the method of LCD voltage generation and
multiplex level. The LCD Clock SFR (LCDCLK, 0x96) configures
timing settings for LCD frame rate and blink rate. LCD pins are
configured for LCD functionality in the LCD Segment Enable
SFR (LCDSEGE, 0x97) and LCD Segment Enable 2 SFR
(LCDSEGE2, 0xED).