MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 120

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

4.1.2 User Privilege Level
MOTOROLA
can separately maintain task control information for each currently executing
workspace area as interrupt handling routines require.
When the M bit is clear, the MC68030 is in the interrupt mode of the supervisor
The value of the M bit in the status register does not affect execution of
the M-bit value and clears it in the SR as part of the exception processing
for interrupts.
All exception processing is performed at the supervisor privilege level. All
the supervisor level. For instance, user programs are not allowed to execute
the STOP instruction or the RESET instruction. To prevent a user program
from entering the supervisor privilege level, except in a controlled manner,
pointer (MSP). The operating system sets the MSP for each task to point to
a task-related area of supervisor data space. This separates task-related su-
pervisor activity from asynchronous, I/O-related supervisor tasks that may
b e o n l y coincidental to the currently executing task. The master stack (MSP)
user task, and the software updates the MSP when a task switch is performed,
providing an efficient means for transferring task-related stack items. The
other supervisor stack (ISP) can be used for interrupt control information and
privilege level, and operation is the same as in the MC68000, MC68008, and
MC68010 supervisor mode. (The processor is in this mode after a reset op-
eration.) All supervisor stack pointer references access the interrupt stack
pointer (ISP) in this mode.
privileged instructions; both master and interrupt modes are at the supervisor
privilege level. Instructions that affect the M bit are MOVE to SR, ANDI to
SR, EORI to SR, ORI to SR, and RTE. Also, the processor automatically saves
bus cycles generated during exception processing are supervisor references,
and all stack accesses use the active supervisor stack pointer.
The user level is the lower privilege level. The privilege level is determined
by the S bit of the status register; if the S bit is clear, the processor executes
instructions at the user privilege level.
have important system effects are privileged and can only be executed at
instructions that can alter the S bit in the status register are privileged. The
TRAP #n instruction provides controlled access to operating system services
for user programs.
Most instructions execute at either privilege level, but some instructions that
MC68030 USER'S MANUAL
4-3
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