MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 422

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
10.4.2 Coprocessor Response Primitive General Format
The M68000 coprocessor response primitives are encoded in a 16-bit word
that is transferred to the main processor through the response CIR. Figure
The encoding of bits [0-12] of a coprocessor response primitive depends on
the individual primitive. Bits [13-15], however, specify optional additional
coprocessor can transfer several response primitives to the main processor
the main processor immediately passes the current value in its program
When an undefined primitive or a primitive that requests an illegal operation
to 10.5.2
these response primitives, however, the main processor passes the program
operations that apply to most of the primitives defined for the M68000 co-
processor interface.
cessor. When the main processor reads a response primitive from the re-
sponse CIR with the come again bit set to one, it performs the service indicated
during the execution of a single coprocessor instruction.
main processor reads a primitive with the PC bit set from the response CIR,
counter to the instruction address CIR as the first operation in servicing the
primitive request. The value in the program counter is the address of the
defined for the M68000 coprocessor interface.
cessing for either an F-line emulator or a protocol violation exception (refer
counter to the instruction address CIR before it initiates exception processing.
10-22 shows the format of the coprocessor response primitives.
Bit [15], the CA bit, specifies the "come again" operation of the main pro-
by the primitive and then reads the response CIR again. Using the CA bit, a
Bit [4], the PC bit, specifies the pass program counter operation. When the
F-line operation word of the coprocessor instruction currently executing. The
PC bit is implemented in all of the coprocessor response primitives currently
is passed to the main processor, the main processor initiates exception pro-
When the main processor initiates a cpGEN instruction that can be executed
first primitive returned by the coprocessor. Since the main processor pro-
I cA I Pc I 0R I
concurrently with main processor instructions, the PC bit is usually set in the
15
14
Main-Processor-Detected Exceptions).
Figure 10-22. Coprocessor Response Primitive Format
13
12
FoNcT,0N
MC68030 USER'S MANUAL
8
I
7
If the PC bit is set in one of
PARAMETE,
10-35
0
1 (