MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 155

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

6
6-18
the cache entry at address $0C, which is filled using a single-entry load
The processor does not assert CBREQ if any of the following conditions exist:
The MC68030 does not assert CBREQ during the first portion of a
access if the remainder of the access does not correspond to the same cache
access is at address $OF. With a 32-bit port, the first access corresponds to
operation. The second access, at address $10 corresponding to the second
cache line, requests a burst fill and the processor asserts CBREQ. During this
burst operation, long words $10, $14, $18, and $1C are all filled in that order.
Additionally, the assertion of CIIN and BERR and the premature negation of
CBACK affect burst operation as described in the following paragraphs.
line. Figure 6-13 shows an example in which the first portion of a misaligned
• The MMU has inhibited caching for the current page
• The cycle is for the first access of an operand that spans two cache lines
The appropriate cache is not enabled
The cache freeze bit for the appropriate cache is set
The current operation is the read portion of a read-modify-write oper-
Burst filling for the cache is not enabled
ation
(crosses a modulo 16 boundary)
Figure 6-13. Deferred Burst Filling Example
Ib'°H°'+'31
I
$10
BURST REQUESTED
$00
SECOND CYCLE -
MC68030 USER'S MANUAL
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IIIIIIIILI
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I
$14
$04
THE REMAINING CACHE ENTRIES FDR SECOND BLOCK ARE 8URSTED
$18
$08
I
FIRST LONG WORD CACHED -
I
$1C
$0C
NO DURST REQUEST
misaligned
MOTOROLA
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I
I