MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 210

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
10) ASSERT DATA BUFFER ENABLE (DBEN)
4) DRIVE FUNCTION CODE ON FCO-FC2
2) SET R/WTO READ
3) DRIVE ADDRESS ON AO-A31
5) DRIVE SIZE (SIZO-SIZ1) (FOUR BYTES)
6) CACHE INHIBIT OUT (CLOUT) BECOMES VALID
7) ASSERT ADDRESS STROBE ( ~ )
8) ASSERT CACHE BURST REQUEST (CBREQ) (IF BURST POSSIBLE)
9) ASSERT DATA STROBE ( ~ )
2) LATCH DATA
3) NEGATE AS AND 05
4) NEGATE DBEN
I) ASSERT ECSIOCS FOR 0NE-HALF CLOCK
1) SAMPLE CACHE INHIBIT IN (CIIN)
AND CACHE BURST ACKNOWLEDGE (CBACK)
State 0
State 1
The read cycle starts with SO. The processor drives ECS low, indicating the
operand operation, OCS is driven low at the same time. During SO, the
TTx register.
four long words of the cache entry are invalid, (i.e., four long words can
beginning of an external cycle. When the cycle is the first cycle of a read
processor places a valid address on A0-A31 and valid function codes on
FC0-FC2. The function codes select the address space for the cycle. The
processor drives R/W high for a read cycle and drives DBEN inactive to
disable the data buffers. SIZ1-SIZ0 become valid, indicating the number
of bytes to be transferred. CLOUT also becomes valid, indicating the state
of the M M U CI bit in the address translation descriptor or in the appropriate
One-half clock later in $1, the processor asserts AS, indicating that the
address on the address bus is valid. The processor also asserts DS during
$1. If the burst mode is enabled for the appropriate on-chip cache and alt
be read in), CBREQ is asserted. In addition, the ECS (and OCS, if asserted)
signal is negated during $1.
Figure 7-31. Synchronous Long-Word Read Cycle Flowchart - -
START NEXT CYCLE
ADDRESS DEVICE
ACQUIRE DATA
PROCESSOR
MC68030 USER'S MANUAL
No Burst Allowed
2) PLACE DATA ON 00-031
3) ASSERT SYNCHRONOUS TERMINATION (STERM)
1) DECODE ADDRESS
2) NEGATE STERM
1) REMOVE DATA FROM D0-O3!
EXTERNAL DEVICE
TERMINATE CYCLE
PRESENT DATA
7-49
m