MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 542

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

12.4.2 Burst Mode Cycles
MOTOROLA
the MC68030 has the capability to initiate bus cycles and then abort them
Another way to optimize the CPU to memory access times in a system is to
tions can be used to calculate the exact access times.
The memory access times for burst mode bus cycles follow the above equa-
tions for the first access only. For the subsequent (second, third, and fourth)
Architectural tradeoffs include the width of the burst memory and the type
values as a base but have additional clock periods added in. The second
devices in the system may require qualification of the access with AS since
use a clock frequency less than the rated maximum of the specific MC68030
device. Table 12-3 provides calculated tAVDV (see Equation 12-7 of Table
clock frequencies. If the system uses other clock frequencies, the above equa-
accesses, the m e m o r y access time calculations depend on the architecture
of the burst mode memory system.
of memory used. If the memory is 128 bits wide, the subsequent operand
accesses do not affect the critical timing paths. For example, if a 3-1-1-1 burst
accesses 128-bit-wide memory, the first access is governed by the equations
in Table 12-2 for N equal to three. The subsequent accesses also use these
before the assertion of AS.
12-2) results for an MC68030RC16 and MC68030RC20 operating at various
2 Clock
3 Clock Synchronous
3 Clock Asynchronous
4 Clock
4 Clock Asynchronous
5 Clock Synchronous
5 Clock Asynchronous
6 Clock Synchronous
6 Clock Asynchronous
T a b l e 12-3, C a l c u l a t e d t A V D V V a l u e s for O p e r a t i o n at F r e q u e n c i e s
Cycle (N) and Type
Clocks Per Bus
Synchronous
Less T h a n or Equal to t h e CPU M a x i m u m F r e q u e n c y Rating
Synchronous
Equation 12-7 tAVDV
MC68030 USER'S MANUAL
Wait
States 16.67 MHz
0
0
2
3
4
3
1
1
2
Clock at
301
121
181
241
241
301
121
181
MC68030RC20
61
Clock at
20 MHz
246
246
146
146
196
196
46
96
96
16.67 MHz
Clock at
248
248
308
128
128
188
308
188
68
MC68030RC25
Clock at
20 MHz
203
253
253
103
103
153
203
153
53
Clock at
25 MHz
158
158
198
198
118
78
78
118
38
12-17
1 2