MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 445

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

10
10.4.19 Take Mid-Instruction Exception Primitive
10-58
tion exception stack frame format. This primitive applies to general and con-
take pre-instruction exception primitive. This protocol allows the main pro-
that can be executed concurrently with the main processor and that support
cessor instruction is initiated, the processor usually requires the instruction
the exception occurred. A coprocessor can record the instruction address by
setting PC = 1 in one of the primitives it uses before releasing the main pro-
cessor.
The take mid-instruction exception primitive initiates exception processing
ditional category instructions. Figure 10-42 shows the format of the take mid-
This primitive uses the PC bit as previously described. Bits [7-0] contain the
exception vector number used by the main processor to initiate exception
When the main processor receives this primitive, it acknowledges the co-
fer to 10.3.2 Control CIR) to the control CIR. The MC68030 then performs
QUENCE. The vector number for the exception is taken from bits [0-7] of the
cessor to proceed with exception processing related to the previous con-
currently executing coprocessor instruction and then return and reinitiate the
coprocessor instruction during which the exception was signaled. The co-
processor should record the addresses of all general category instructions
exception recovery. Since the exception is not reported until the next copro-
address to determine which instruction the coprocessor was executing when
using a coprocessor-supplied exception vector number and the mid-instruc-
instruction exception primitive.
processing.
processor exception request by writing an exception acknowledge mask (re-
exception processing as described in 8.1 EXCEPTION PROCESSING SE-
primitive and the MC68030 uses the 10-word stack frame format shown in
Figure 10-43.
15
0
PC
Figure 10-42. Take Mid-Instruction Exception Primitive Format
14
0
13 12
1
11
1
MC68030 USER'S MANUAL
10
1
9
0
8
1
7
VECTOR NUMBER
MOTOROLA
0
J