MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 30

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

SECTION 1
MOTOROLA
The MC68030 is a second-generation full 32-bit enhanced microprocessor
from Motorola. The MC68030 is a member of the M68000 Family of devices
that combines a central processing unit (CPU) core, a data cache, an instruc-
tion cache, an enhanced bus controller, and a memory management unit
The MC68030 is upward object code compatible with the earlier members
coprocessor. Also, the internal functional blocks of this microprocessor are
The MC68030 fully supports the nonmultiplexed bus structure of the MC68020,
with 32 bits of address and 32 bits of data. The MC68030 bus has an enhanced
A block diagram of the MC68030 is shown in Figure 1-1. The instructions and
The bus controller manages the transfer of data between the CPU and mem-
INTRODUCTION
speeds beyond 20 MHz. The MC68030 is implemented with 32-bit registers
and data paths, 32-bit addresses, a rich instruction set, and versatile ad-
dressing modes.
of the M68000 Family and has the added features of an on-chip MMU, a data
cache, and an improved bus interface. It retains the flexible coprocessor
support through this interface with the MC68881 or MC68882 floating-point
designed to operate in parallel, allowing instruction execution to be over-
lapped. In addition to instruction execution, the internal caches, the on-chip
MMU, and the external bus controller all operate in parallel.
controller that supports both asynchronous and synchronous bus cycles and
burst data transfers, It also supports the MC68020 dynamic bus sizing mech-
anism that automatically determines device port sizes on a cycle-by-cycle
basis as the processor transfers operands to or from external devices.
data required by the processor are supplied from the internal caches when-
ever possible. The MMU translates the logical address generated by the
processor into a physical address utilizing its address translation cache (ATC).
ory or devices at the physical address.
(MMU) in a single VLSl device. The processor is designed to operate at clock
interface pioneered in the MC68020 and provides full IEEE floating-point
MC68030 USER'S MANUAL
1-1
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