MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 487

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

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11-24
11.6 I N S T R U C T I O N
The only instances for which the size of the operand has any effect are the
tical execution times.
All the following assumptions apply to the times shown in the tables in this
section:
Four
instructions with immediate operands and the ADDA and SUBA instructions.
Unless specified otherwise, immediate byte and word operands have iden-
• All memory accesses occur with two-clock bus cycles and no wait states.
• All operands in memory, including the system stack, are long-word
• A 32-bit bus is used for communications between the MC68030 and
• The data cache is not enabled.
• No exceptions occur (except as specified).
• Required address translations for all external bus cycles are resident in
2.
3.
1.
.
the address translation cache.
aligned.
system memory.
Tail,
Average no-cache case (NCC) when the instruction is not in the cache
Head,
or the cache is disabled and there is no instruction overlap.
values are listed for each instruction and effective address:
Instruction-cache case (CC) when the instruction is in the cache but has
no overlap, and
T I M I N G T A B L E S
MC68030 USER'S MANUAL
MOTOROLA