MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 178

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
CPU32+
If the frame was generated by an interrupt, breakpoint, trap, or instruction exception, the SR
and PC are restored to the values saved on the supervisor stack, and execution resumes at
the restored PC address, with access level determined by the S-bit of the restored SR.
If the frame was generated by a bus error or an address error exception, the entire processor
state is restored from the stack.
5.5 EXCEPTION PROCESSING
An exception is a special condition that pre-empts normal processing. Exception processing
is the transition from normal mode program execution to execution of a routine that deals
with an exception. The following paragraphs discuss system resources related to exception
handling, exception processing sequence, and specific features of individual exception pro-
cessing routines.
5.5.1 Exception Vectors
An exception vector is the address of a routine that handles an exception. The VBR contains
the base address of a 1024-byte exception vector table, which consists of 256 exception
vectors. Sixty-four vectors are defined by the processor, and 192 vectors are reserved for
user definition as interrupt vectors. Except for the reset vector, which is two long words, each
vector in the table is one long word. Refer to Table 5-16 for information on vector assign-
ment.
All exception vectors, except the reset vector, are located in supervisor data space. The
reset vector is located in supervisor program space. Only the initial reset vector is fixed in
the processor memory map. When initialization is complete, there are no fixed assignments.
Since the VBR stores the vector table base address, the table can be located anywhere in
memory. It can also be dynamically relocated for each task executed by an operating sys-
tem.
Each vector is assigned an 8-bit number. Vector numbers for some exceptions are obtained
from an external device; others are supplied by the processor. The processor multiplies the
vector number by 4 to calculate vector offset, then adds the offset to the contents of the VBR.
The sum is the memory address of the vector.
5.5.1.1 TYPES OF EXCEPTIONS. An exception can be caused by internal or external
events.
An internal exception can be generated by an instruction or by an error. The TRAP, TRAPcc,
TRAPV, BKPT, CHK, CHK2, RTE, and DIV instructions can cause exceptions during normal
execution. Illegal instructions, instruction fetches from odd addresses, word or long-word
operand accesses from odd addresses, and privilege violations also cause internal excep-
tions.
Sources of external exception include interrupts, breakpoints, bus errors, and reset
requests. Interrupts are peripheral device requests for processor action. Breakpoints are
used to support development equipment. Bus error and reset are used for access control
and processor restart.
5-36
MC68360 USER’S MANUAL
MOTOROLA
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