MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 602

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor, Inc.
Serial Management Controllers (SMCs)
the buffer. Thus, MAX_IDL provides a convenient way to demarcate frames in the UART
mode. If the MAX_IDL functionality is not desired, the user should program MAX_IDL to
$0000, and the buffer will never be closed, regardless of the number of idle characters
received. A character of idle is calculated as the following number of bit times: 1 + data
length (5 to 14) + 1 (if parity bit is used) + number of stop bits (1 or 2). Example: for 8 data
bits, no parity, and 1 stop bit, the character length is 10 bits.
IDLC. This value is used by the RISC to store the current idle counter value in the MAX_IDL
timeout process. IDLC is a down-counter; it does not need to be initialized or accessed by
the user.
BRKLN. This value is used to store the length of the last break character received. This
value is the length in bits of that character. Example: If the receive pin is low for 257 bit times,
BRKLN will show the value $0101. BRKLN is accurate to within one character unit of bits.
For example, for 8 data bits, no parity, 1 stop bit, and 1 start bit, BRKLN is accurate to within
10 bits.
BRKEC. This counter counts the number of break conditions that occurred on the line. Note
that one break condition may last for hundreds of bit times, yet this counter is incremented
only once during that period.
BRKCR. The SMC UART controller will send an a break character sequence whenever a
STOP TRANSMIT command is given. The number of break characters sent by the UART
controller is determined by the value in BRKCR. In the case of 8 data bits, no parity, 1 stop
bit, and 1 start bit, each break character is 10 bits in length and consists of all zeros.
7.11.7.4 SMC UART TRANSMISSION PROCESSING. The UART transmitter is designed
to work with almost no intervention from the CPU32+ core. When the CPU32+ core enables
the SMC transmitter, it will start transmitting idles. The SMC immediately polls the first BD
in the transmit channel’s BD ring, and thereafter once every character time, depending on
the character length (i.e., every 7 to 16 serial clocks). When there is a message to transmit,
the SMC will fetch the data from memory and start transmitting the message.
When a BD’s data has been completely written to the transmit FIFO, the SMC writes the
message status bits into the BD and clears the R-bit. An interrupt is issued if the I-bit in the
BD is set. If the next Tx BD is ready, the data from its data buffer will be appended to the
previous data and transmitted out on the transmit pin, with no gaps occurring between buff-
ers. If the next Tx BD is not ready, the SMC will start transmitting idles and wait for the next
Tx BD to become ready.
By appropriately setting the I-bit in each BD, interrupts can be generated after the transmis-
sion of each buffer, a specific buffer, or each block. The SMC will then proceed to the next
BD in the table.
If the CM bit is set in the Tx BD, the R-bit will not be cleared, allowing the associated data
buffer to be retransmitted automatically when the CP next accesses this data buffer. For
instance, if a single Tx BD is initialized with the CM bit set and the W-bit set, the data buffer
will be continuously transmitted until the user clears the R-bit of the BD.
7-278
MC68360 USER’S MANUAL
MOTOROLA
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