MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 704

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

CPM Interrupt Controller (CPIC)
7.15.5.3 CPM INTERRUPT MASK REGISTER (CIMR). Each bit in the 32-bit read-write
CIMR corresponds to a CPM interrupt source. The user masks an interrupt by clearing the
corresponding bit in the CIMR and enables an interrupt by setting the corresponding bit in
the CIMR. When a masked CPM interrupt occurs, the corresponding bit in the CIPR is still
set, regardless of the CIMR bit, but no interrupt request is passed to the CPU32+ core.
If a CPM interrupt source is requesting interrupt service when the user clears its CIMR bit,
the request will cease. If its CIMR bit is later set by the user, a previously pending interrupt
request will be processed by the CPU32+ core, according to its assigned priority. The CIMR
can be read by the user at any time. The CIMR is cleared at reset.
7.15.5.4 CPM INTERRUPT IN-SERVICE REGISTER (CISR). Each bit in the 32-bit read-
write CISR corresponds to a CPM interrupt source. In a vectored interrupt environment, the
CPIC sets the CISR bit when the vector number corresponding to the CPM interrupt source
is passed during an interrupt acknowledge cycle. The user’s interrupt service routine must
clear this bit after servicing is complete. (If an event register exists for this peripheral, its bits
would normally be cleared as well.) To clear a bit in the CISR, the user writes a one to that
bit. Since the user can only clear bits in this register, bits written as zeros will not be affected.
The CISR is cleared at reset.
7-380
PC0
PC4
PC0
PC4
31
15
31
15
SCC1
SCC1
PC5
PC5
30
14
30
14
SCC2
SCC2
29
13
29
13
—
The SCC CIMR bit positions are NOT affected by the relative pri-
ority between SCCs (as determined by the SCxP and SPS bits
in the CICR).
To clear bits that were set by multiple interrupt events, the user
must clear all the unmasked events in the corresponding event
register.
If a bit in the CIMR is masked at the same time that the corre-
sponding CIPR bit causes an interrupt request to the IMB, then
the interrupt is not processed, but the error vector is issued if the
interrupt acknowledge cycle occurs with no other CPM interrupts
pending. Thus, the user should always include an error vector
routine, even if it just contains the RTE instruction.
The error vector cannot be masked.
—
TIMER3
TIMER3
SCC3
SCC3
28
12
28
12
SCC4
SCC4
PC6
PC6
27
11
27
11
Freescale Semiconductor, Inc.
For More Information On This Product,
PC1
PC7
PC1
PC7
26
10
26
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
TIMER1
TIMER1
PC8
PC8
25
25
9
9
NOTES
PC2
PC2
24
24
—
—
8
8
TIMER4
TIMER4
PC3
PC3
23
23
7
7
SDMA
SDMA
PC9
PC9
22
22
6
6
IDMA1
IDMA1
SPI
SPI
21
21
5
5
IDMA2
IDMA2
SMC1
SMC1
20
20
4
4
SMC2 /
SMC2 /
PIP
PIP
19
19
—
—
3
3
TIMER2
TIMER2
PC10
PC10
18
18
2
2
MOTOROLA
PC11
PC11
R–TT
R–TT
171
171
1
1
16
—
16
—
—
—
0
0