MC68MH360ZP33L Freescale Semiconductor, MC68MH360ZP33L Datasheet - Page 436

• Manufacturer Part Number: MC68MH360ZP33L
• Description: IC MPU 32BIT QUICC 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360ZP33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Serial Communication Controllers (SCCs)
Bits 63–49, 31—Reserved
GDE—Glitch Detect Enable
TCRC—Transparent CRC (Valid for a Totally Transparent Channel Only)
REVD—Reverse Data (Valid for a Totally Transparent Channel Only)
TRX—Transparent Receiver
7-112
This bit determines whether the SCC will look for glitches on the external receive and
transmit serial clock lines provided to this SCC. If this feature is enabled, the presence of
a glitch will be reported in the SCC event register. Whether or not GDE is set, the SCC
always attempts to clean up the clocks that it uses internally via a Schmitt trigger on the
input lines.
These bits select the type of frame checking that is provided on the transparent channels
of this SCC (either the receiver, transmitter, or both as defined by TTX and TRX). Al-
though this configuration selects a frame check type, the actual decision to send the frame
check is made in the Tx BD. Thus, it is not required to send a frame check in transparent
mode. If a frame check is not used, the user may simply ignore the frame check errors
that are generated on the receiver.
The QUICC SCCs offer totally transparent operation. However, to increase flexibility, to-
tally transparent operation is not configured with the MODE bits, but with the TTX and
TRX bits. This gives the user the opportunity to implement unique applications, such as
an SCC transmitter configured to UART and the receiver configured to totally transparent
operation. To do this, set MODE = UART, TTX = 0, and TRX = 1.
0 = No glitch detection is performed. This option should be chosen if the external serial
1 = Glitch detection is performed with a maskable interrupt generated in the SCC event
00 = 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1)
01 = CRC16 (BISYNC). (X16 + X15 + X2 + 1)
10 = 32-bit CCITT CRC (Ethernet and HDLC). (X32 + X26 + X23 + X22 + X16 + X12
11 = Reserved
0 = Normal operation.
1 = When set, this bit will cause the totally transparent channels on this SCC (either
0 = Normal operation.
1 = The receiver operates in totally transparent mode, regardless of the protocol se-
clock exceeds the limits of the glitch detection logic (6.25 MHz assuming a 25-MHz
system clock). This option should also be chosen if the SCC clock is provided from
one of the internal baud rate generators. Lastly, this option should be chosen if ex-
ternal clocks are used and it is more important to minimize power consumption
than to watch for glitches.
register.
the receiver, transmitter, or both as defined by TTX and TRX) to reverse the bit or-
der, transmitting the MSB of each octet first. See 7.10.20.11 BISYNC Mode Reg-
ister (PSMR) for the method of reversing the bit order in the BISYNC protocol.
lected for the transmitter in the MODE bits.
+ X11 + X10 + X8 + X7 + X5 + X4 + X2 + X1 +1)
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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