ISP1583BSUM ST-Ericsson Inc, ISP1583BSUM Datasheet - Page 21
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ISP1583BSUM
Manufacturer Part Number
ISP1583BSUM
Description
IC USB PERIPH CONTROLLER 64HVQFN
Manufacturer
ST-Ericsson Inc
Datasheet
1.ISP1583BSUM.pdf
(100 pages)
Specifications of ISP1583BSUM
Controller Type
USB Peripheral Controller
Interface
Parallel/Serial
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
47mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-1886-2
ISP1583BS,518
ISP1583BS-T
ISP1583BS,518
ISP1583BS-T
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NXP Semiconductors
ISP1583_7
Product data sheet
8.13.2 Interrupt control
8.14 V
Bit GLINTENA in the Mode register is a global interrupt enable or disable bit. The behavior
of this bit is given in
The following illustrations are only applicable for level trigger.
Event A: When an interrupt event occurs (for example, SOF interrupt) with bit GLINTENA
set to logic 0, an interrupt will not be generated at pin INT. It will, however, be registered in
the corresponding Interrupt register bit.
Event B: When bit GLINTENA is set to logic 1, pin INT is asserted because bit SOF in the
Interrupt register is already set.
Event C: If the firmware sets bit GLINTENA to logic 0, pin INT will still be asserted. The
bold line shows the desired behavior of pin INT.
Deassertion of pin INT can be achieved either by clearing all the bits in the Interrupt
register or the DMA Interrupt Reason register, depending on the event.
Remark: When clearing an interrupt event, perform write to all the bytes of the register.
For more information on interrupt control, see
Section
The V
with bit CLKAON set to logic 0 (clock off option).
To detect whether the host is connected or not, that is V
a 1 F electrolytic or tantalum capacitor must be added to damp the overshoot on plug in.
Fig 6.
BUS
BUS
sensing
9.5.1.
Pin INT: HIGH = deassert; LOW = assert (individual interrupts are enabled).
Behavior of bit GLINTENA
pin is one of the ways to wake up the clock when the ISP1583 is suspended
INT pin
occurs, for example,
Figure
Rev. 07 — 22 September 2008
an interrupt event
(during this time,
GLINTENA = 0
SOF asserted)
6.
A
GLINTENA = 1
SOF asserted
B
Section
Hi-Speed USB peripheral controller
9.2.2,
BUS
GLINTENA = 0
SOF asserted
sensing, a 1 M resistor and
Section 9.2.5
C
004aaa394
© NXP B.V. 2008. All rights reserved.
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