LAN9420I-NU SMSC, LAN9420I-NU Datasheet - Page 127

• Manufacturer Part Number: LAN9420I-NU
• Description: IC ETHERNET CTRLR SGL 128VTQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9420I-NU

• Controller Type: Ethernet Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 145mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.6 V
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 10/100 Base-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1085

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
4.4.6
31-16
15-11
BITS
10-6
5-2
1
0
RESERVED
PHY Address
For every access to this register, this field must be set to 00001b.
MII Register Index (MIIRINDA)
These bits select the desired MII register in the PHY.
RESERVED
MII Write (MIIWnR)
Setting this bit tells the PHY that this will be a write operation using the MII
data register. If this bit is not set, this will be a read operation, packing the
data in the MII data register.
MII Busy (MIIBZY)
This bit must be polled to determine when the MII register access is
complete. This bit must read a logical 0 before writing to this register or to
the MII data register. The LAN driver software must set (1) this bit in order
for the Host system to read or write any of the MII PHY registers.
During a MII register access, this bit will be set, signifying a read or write
access is in progress. The MII data register must be kept valid until the
MAC clears this bit during a PHY write operation. The MII data register is
invalid until the MAC has cleared this bit during a PHY read operation.
MII Access Register (MII_ACCESS)
This register is used to control the management cycles to the internal PHY.
Offset:
DESCRIPTION
0094h
DATASHEET
127
Size:
32 bits
R/W/SC
TYPE
R/W
R/W
R/W
RO
RO
Revision 1.4 (12-17-08)
DEFAULT
00000b
00000b
0b
0b
-
-