LAN9420I-NU SMSC, LAN9420I-NU Datasheet - Page 72

IC ETHERNET CTRLR SGL 128VTQFP

LAN9420I-NU

Manufacturer Part Number
LAN9420I-NU
Description
IC ETHERNET CTRLR SGL 128VTQFP
Manufacturer
SMSC
Type
Single Chip MAC and PHY Controllerr
Datasheets

Specifications of LAN9420I-NU

Controller Type
Ethernet Controller
Interface
PCI
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
145mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 MB, 100 MB
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.6 V
Maximum Operating Temperature
+ 85 C
Ethernet Connection Type
10/100 Base-T
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
638-1085

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Revision 1.4 (12-17-08)
3.6.6.3
3.6.7
3.6.8
3.6.8.1
Half vs. Full-Duplex
Half-duplex operation relies on the CSMA/CD (Carrier Sense Multiple Access / Collision Detect)
protocol to handle network traffic and collisions. In this mode, the carrier sense signal, CRS, responds
to both transmit and receive activity.
a collision results.
In full-duplex mode, the PHY is able to transmit and receive data simultaneously. In this mode, CRS
responds only to receive activity. The CSMA/CD protocol does not apply and collision detection is
disabled.
HP Auto-MDIX
HP Auto-MDIX facilitates the use of CAT-3 (10 BASE-T) or CAT-5 (100 BASE-T) media UTP
interconnect cable without consideration of interface wiring scheme. If a user plugs in either a direct
connect LAN cable, or a cross-over patch cable, as shown in
LAN9420/LAN9420i Auto-MDIX PHY is capable of configuring the TPO+/TPO- and TPI+/TPI- twisted
pair pins for correct transceiver operation.
The internal logic of the device detects the TX and RX pins of the connecting device. Since the RX
and TX line pairs are interchangeable, special PCB design considerations are needed to accommodate
the symmetrical magnetics and termination of an Auto-MDIX design.
The Auto-MDIX function can be disabled through an internal register 27.15, or the external
AUTOMDIX_EN configuration strap. When Auto-MDIX mode is disabled (27.15 = 1), the TX and RX
pins can be configured as desired using the MDIX State (27.13) control bit.
PHY Power-Down Modes
There are 2 power-down modes for the PHY as discussed in the following sections.
General Power-Down
This power-down is controlled by register 0, bit 11. In this mode the PHY, except the management
interface, is powered-down and stays in that condition as long as PHY register bit 0.11 is HIGH. When
bit 0.11 is cleared, the PHY powers up and is automatically reset. Please refer to
Control Register," on page 136
Not Used
Not Used
Not Used
Not Used
TPO+
TPO-
Figure 3.27 Direct Cable Connection vs. Cross-Over Cable Connection
TPI+
TPI-
RJ-45 8-pin straight-through
1
2
3
4
5
6
7
8
for 10BASE-T/100BASE-TX
Direct Connect Cable
signaling
1
2
3
4
5
6
7
8
for additional information on this register.
TPO+
TPO-
TPI+
Not Used
Not Used
TPI-
Not Used
Not Used
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
DATASHEET
In this mode, If data is received while the PHY is transmitting,
72
Not Used
Not Used
Not Used
Not Used
TPO+
TPO-
TPI+
TPI-
1
2
3
4
5
6
7
8
RJ-45 8-pin cross-over for
10BASE-T/100BASE-TX
Cross-Over Cable
signaling
Figure 3.27 on page
1
2
3
4
5
6
7
8
TPO+
TPO-
TPI+
Not Used
Not Used
TPI-
Not Used
Not Used
SMSC LAN9420/LAN9420i
Section 4.5.1, "Basic
Datasheet
72, the

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