LAN9420I-NU SMSC, LAN9420I-NU Datasheet - Page 25

• Manufacturer Part Number: LAN9420I-NU
• Description: IC ETHERNET CTRLR SGL 128VTQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9420I-NU

• Controller Type: Ethernet Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 145mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.6 V
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 10/100 Base-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1085

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i
3.2.2
3.2.3
3.2.3.1
Component
PCI
PCI Interface Environments
The PCIB supports only Device operation. It functions as a simple bridge, permitting
LAN9420/LAN9420i to act as a master/target PCI device on the PCI bus. The Host performs PCI
arbitration and is responsible for initializing configuration space for all devices on the bus.
illustrates Device operation.
PCI Master Interface
The PCI Master Interface is used by the DMA engines to directly access the PCI Host’s memory. It is
used by the TX and RX DMA Controllers to access Host descriptor ring elements and Host DMA
buffers. No address translation occurs, as these entities are contained within the Host, which allocates
them within the flat PCI address space.
PCI Master Transaction Errors
In the event of an error during a descriptor read or during a transmit data read, the DMA controller will
generate a Master Bus Error Interrupt (MBERR_INT).
When an MBERR_INT is asserted, all subsequent transactions from the DMAC will be aborted. In
order to cleanly recover from this condition, a software reset or H/W reset must be performed. A
software reset is accomplished by setting the SRST bit of the BUS_MODE register.
Note: It is guaranteed that the MBERR_INT will be reported on the frame upon which the error
occurred as follows:
- Errors on descriptor reads will be aborted immediately.
- Errors on TX data will be reported either upon the data or the close descriptor (if the error
occurs on the last data transfer).
- DMA RX data and descriptor write operations are posted and will therefore not generate the
MBERR_INT.
Bus
PCI
Component
PCI
Figure 3.2 Device Operation
DATASHEET
System
Host
25
LAN9420
PCIB
Revision 1.4 (12-17-08)
Component
PCI
Figure 3.2