LAN9420I-NU SMSC, LAN9420I-NU Datasheet - Page 169

• Manufacturer Part Number: LAN9420I-NU
• Description: IC ETHERNET CTRLR SGL 128VTQFP
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9420I-NU

• Controller Type: Ethernet Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 145mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.6 V
• Maximum Operating Temperature: + 85 C
• Ethernet Connection Type: 10/100 Base-T
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1085

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Chapter 7 Revision History
SMSC LAN9420/LAN9420i
REVISION LEVEL & DATE
(09-23-08)
(07-30-08)
(11-20-08)
Rev. 1.22
Rev. 1.21
Rev. 1.3
Section 3.7.7, "Enabling
Link Status Change (Energy
Detect) Wake Events," on
page 81
Section 4.3.1, "Bus Mode
Register (BUS_MODE)," on
page 104
Table 5.13,
“LAN9420/LAN9420i Crystal
Specifications,” on page 166
Figure 1.2
LAN9420/LAN9420i Internal
Block Diagram on page 11
Figure 1.2
LAN9420/LAN9420i Internal
Block Diagram on page 11
Section 4.5.5, "Auto
Negotiation Advertisement,"
on page 140
Table 4.10, “Standard PCI
Header Registers
Supported,” on page 150
Table 4.10, “Standard PCI
Header Registers
Supported,” on page 150
Section 3.5.5.1, "RX
Checksum Calculation," on
page 63
Section 3.5.4, "Wakeup
Frame Detection," on
page
"MAC Control Register
(MAC_CR)," on page 119
Section 4.4.12, "Wakeup
Control and Status Register
(WUCSR)," on page 133
Section 5.9, "Clock Circuit,"
on page 166
SECTION/FIGURE/ENTRY
57,
Table 7.1 Customer Revision History
Section 4.4.1,
All
DATASHEET
Added PCI SIG certification logo to cover
169
Fixed various typos.
Corrected second sentence of step 3: “This is done
by setting the EDPWRDOWN bit in the PHY’s
Mode Control/Status register.”
Added DBO and BLE bit definitions.
Updated max ESR value to 50 Ohms.
Fixed error: Changed “To option..” text to
“(optional)” and moved it to the end of the
descriptions.
- Changed “To option..” text to “(optional)” and
moved it to the end of the descriptions.
- Removed “To” from “To Ethernet”.
- Placed bi-directional arrows on EEPROM,
GPIO/LED, and PHY blocks.
Changed bits 9 and 15 to RESERVED with a
default value of 0b.
Added note to default value of Revision ID stating
that the default value is dependent on device
revision.
Changed default values of Min_Gnt and Max_Lat
to 02h and 04h, respectively.
Changed last line of RX checksum calculation to
“checksum = [B1, B0] + C0 + [B3, B2] + C1 + …
+ [0, BN] + CN-1”
Added note: “When wake-up frame detection is
enabled via the WUEN bit of the
and Status Register
up frame will wake-up the device despite the state
of the Disable Broadcast (BCAST) bit in the
Control Register
Corrected GUE bit description to state: “....A global
unicast frame has the MAC Address [0] bit set to
0.”
Updated Drive Level from 0.5mW to 300uW.
(MAC_CR). “
CORRECTION
(WUCSR), a broadcast wake-
Revision 1.4 (12-17-08)
Wakeup Control
MAC