DP8409AN National Semiconductor, DP8409AN Datasheet - Page 11

• Manufacturer Part Number: DP8409AN
• Description: IC CONTROLLER DYNAMIC RAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8409AN

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 250mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8409AN

Figure 7b ) If CASIN is low when R C goes low CAS will be
DP8409A Functional Mode Descriptions
Automatic CAS Generation
In a normal memory access cycle CAS can be derived from
inputs CASIN or R C If CASIN is high then R C going low
switches the address output drivers from rows to columns
CASIN then going low causes CAS to go low approximately
40 ns later allowing CAS to occur at a predictable time (see
automatically generated following the row to column tran-
sition by about 20 ns (see Figure 7a ) Most DRAMs have a
column address set-up time before CAS (t
b
Fast Memory Access
AC parameters t
minimum delays required between RASIN R C and CASIN
(see Application Brief 9 ‘‘Fastest DRAM Access Mode’’)
MODE 5 AUTOMATIC ACCESS WITH HIDDEN REFRESH
The Auto Access with Hidden Refresh mode has two ad-
vantages over the Externally Controlled Access mode due
to the fact that all outputs except WE are initiated from
RASIN First inputs R C and CASIN are unnecessary and
can be used for other functions (see Refreshing below)
Secondly because the output control signals are derived
internally from one input signal (RASIN) timing-skew prob-
lems are reduced thereby reducing memory access time
substantially or allowing use of slower DRAMs The auto-
matic access features of Mode 5 (and Mode 6) of the
DP8409A make DRAM accessing appear essentially ‘‘stat-
ic’’
Automatic Access Control
The major disadvantage of DRAMs compared to static
RAMs is the complex timing involved First a RAS must
occur with the row address previously set up on the multi-
plexed address bus After the row address has been held
for t
column address is set up and then CAS occurs This is all
performed automatically by the DP8409A in this mode
Provided the input address is valid as ADS goes low RASIN
can go low any time after ADS This is because the selected
RAS occurs typically 27 ns later by which time the row ad-
dress is already valid on the address output of the
DP8409A The Address Set-Up time (t
DRAMs The DP8409A in this mode (with ADS and RASIN
edges simultaneously applied) produces a minimum t
0 ns This is true provided the input address was valid t
before ADS went low (see Figure 8a )
Next the row address is disabled after t
mum) in most DRAMs t
The column address is then set up and t
occurs The only other control input required is WIN When
a write cycle is required WIN must go low at least 30 ns
before CAS is output low
This gives a total typical delay from input address valid to
RASIN (15 ns) to RAS (27 ns) to rows held (50 ns) to
columns valid (25 ns) to CAS (23 ns)
125 ns from RASIN) All of these typcial figures are for
heavy capacitive loading of approximately 88 DRAMs
10 ns In other words a t
RAH
(the Row-Address hold-time of the DRAM) the
DIF1
t
DIF2
RAH
ASC
may be used to determine the
minimum is less than 30 ns
greater than 0 ns is safe
ASR
e
) is 0 ns on most
RAH
ASC
140 ns (that is
ASC
(30 ns mini-
) of 0 ns or
later CAS
ASR
ASA
of
11
Figure 9 illustrates the refresh alternatives in Mode 5 If a
(Continued)
This mode is therefore extremely fast The external timing is
greatly simplified for the memory system designer the only
system signal required is RASIN
Refreshing
Because R C and CASIN are not used in this mode R C
becomes RFCK (refresh clock) and CASIN becomes RGCK
(RAS generator clock) With these two signals it is possible
to peform refreshing without extra ICs and without holding
up the processor
One refresh cycle must occur during each refresh clock pe-
riod and then the refresh address must be incremented to
the next refresh cycle As long as 128 rows are refreshed
every 2 ms (one row every 16 s) all 16k and 64k DRAMs
will be correctly refreshed The cycle time of RFCK must
therefore be less than 16
internal refresh-request flip-flop First the DP8409A will at-
tempt to perform a hidden refresh so that the system
throughput will not be affected If during the time RFCK is
high CS on the DP8409A goes high and RASIN occurs a
hidden refresh will occur In this case RASIN should be
considered a common read write strobe In other words if
the processor is accessing elsewhere (other than the
DRAMs) while RFCK is high the DP8409A will perform a
refresh The refresh counter is enabled to the address out-
puts whenever CS goes high with RFCK high and all RAS
outputs follow RASIN If a hidden refresh is taking place as
RFCK goes low the refresh continues At the start of the
hidden refresh the refresh-request flip-flop is reset so no
further refresh can occur until the next RFCK period starts
with the positive-going edge of RFCK Refer to Figure 9
To determine the probability of a Hidden Refresh occurring
assume each system cycle takes 400 ns and RFCK is high
for 8 s then the system has 20 chances to not select the
DP8409A If during this time a hidden refresh did not occur
then the DP8409A forces a refresh while RFCK is low but
the system chooses when the refresh takes place After
RFCK goes low (and the internal-request flip-flop has not
been reset) RF I O goes low indicating that a refresh is
requested to the system Only when the system acknowl-
edges this request by setting M2 (RFSH) low does the
DP8409A initiate a forced refresh (which is performed auto-
matically) Refer to Mode 1 and Figure 3 The internal re-
fresh request flip-flop is then reset
hidden refresh has occurred and CS again goes high before
RFCK goes low the chip is deselected All the control sig-
nals go high-impedance high (logic ‘‘1’’) and the address
outputs go TRI-STATE until CS again goes low This mode
(combined with Mode 1) allows very fast access and auto-
matic refreshing (possibly not even slowing down the sys-
tem) with no extra ICs Careful system design can and
should provide a higher probability of hidden refresh occur-
ring The duty cycle of RFCK need not be 50-percent in
fact the low-time should be designed to be a minimum This
is determined by the worst-case time (required by the sys-
tem) to respond to the DP8409A’s forced-refresh request
s RFCK going high sets an