DP8409AN National Semiconductor, DP8409AN Datasheet - Page 17

• Manufacturer Part Number: DP8409AN
• Description: IC CONTROLLER DYNAMIC RAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8409AN

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 250mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8409AN

REFRESH (Continued)
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T
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TRI-STATE
t
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Symbol
RFHRV
ROHNC
RLEOC
RHEOC
RGEOB
MCEOB
RST
CTL
RFCKL H
RGCKL
RGCKH
FRQL
FRQH
RGRL
RGRH
RQHRF
RFRH
RFSRG
CSCT
CSRL
ZH
HZ
ZL
LZ
HZH
HHZ
Switching Characteristics DP8409A DP8409A-3
V
of 22 DRAMs each or 88 DRAMs including trace capacitance These values are Q0– Q8 C
150 pF WE C
closed unless otherwise noted and R1 and R2 are 4 7 k
with all outputs switching
CC
e
5 0V
RFSH High to Row Address Valid
RAS High to New Count Valid
RASIN Low to End-of-Count Low
RASIN High to End-of-Count High
RGCK Low to End-of-Burst Low
Mode Change to End-of-Burst High
Counter Reset Pulse Width
RF I O Low to Counter Outputs All Low
Minimum Pulse Width of RFCK
Period of RAS Generator Clock
Minimum Pulse Width Low of RGCK
Minimum Pulse Width High of RGCK
RFCK Low to Forced RFRQ Low
RGCK Low to Forced RFRQ High
RGCK Low to RAS Low
RGCK Low to RAS High
RFSH Hold Time from RFSH RQST (RF I O)
RFSH High to RAS High (ending forced RFSH)
RFSH Low Set-Up to RGCK Low (Mode 1)
CS High to RFSH Counter Valid
CS Low to Access RASIN Low
CS Low to Address Output High from Hi-Z
CS High to Address Output Hi-Z from High
CS Low to Address Output Low from Hi-Z
CS High to Address Output Hi-Z from Low
CS Low to Control Output High from
Hi-Z High
CS High to Control Output Hi-Z High
from High
g
L
5% 0 C
e
500 pF CAS C
s
T
Parameter
A s
70 C (unless otherwise noted) (Notes 2 4 5) The output load capacitance is typical for 4 banks
L
e
600 pF (unless otherwise noted) See Figure 11 for test load Switches S1 and S2 are
Figures 2 3
Figures 2 4
Figure 2
Figure 2
Figure 9
Figure 3
Figure 3
Figure 3
Figure 3
Figure 3
Figure 3
Figure 9
Figures 9 12
Figures 9 12
Figures 9 12
Figures 9 12
Figures 9 12
Figures 9 12
C
C
See Mode 5 Descrip
R1
R2
R1
R1
R2
R2
C
C
C
C
See Mode 1 Descrip
See Mode 1 Descrip
C
C
C
unless otherwise noted Maximum propagation delays are specified
L
L
L
L
L
L
L
L
L
e
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e
17
e
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Conditions
50 pF Figure 2
50 pF Figure 2
50 pF Figure 4
50 pF Figure 4
50 pF Figure 3
50 pF Figure 3
15 pF
15 pF
15 pF
3 5k R2
1k S1 Open
3 5k R2
1k S2 Open
750
750
S1 Open
S1 Open
e
e
1 5k
1 5k
(Continued)
Min
100
100
2T
70
35
35
50
40
55
35
30
DP8409A
Typ
45
30
20
50
65
60
80
55
35
20
35
25
50
40
L
e
Max
100
110
60
55
80
80
95
75
30
75
95
85
70
60
40
60
50
80
75
500 pF RAS0– RAS3 C
Min
100
100
70
40
40
50
40
2T
55
40
30
DP8409A-3
Typ
45
30
20
50
65
60
80
55
35
20
35
25
50
40
Max
100
125
70
55
80
80
95
75
30
75
95
85
75
60
40
60
50
80
75
L
Units
e
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns