DP8409AN National Semiconductor, DP8409AN Datasheet - Page 9

• Manufacturer Part Number: DP8409AN
• Description: IC CONTROLLER DYNAMIC RAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8409AN

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 250mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8409AN

DP8409A Functional Mode Descriptions
MODE 3b EXTERNALLY CONTROLLED ALL-RAS
WRITE
To select this mode B1 and B0 must first have been set to
11 in Mode 7 This mode is useful at system initialization
but under processor control The memory address is provid-
ed by the processor which also performs the incrementing
All four RAS outputs follow RASIN (supplied by the proces-
sor) strobing the row address into the DRAMs R C can
now go low while CASIN may be used to control CAS (as in
the Externally Controlled Access mode) so that CAS
strobes the column address contents into the DRAMs At
this time WE should be low causing the data to be written
into all four banks of DRAMs At the end of the write cycle
the input address is incremented and latched by the
DP8409A for the next write cycle This method is slower
than Mode 3a since the processor must perform the incre-
menting and accessing Thus the processor is occupied dur-
ing RAM initialization and is not free for other initialization
FIGURE 6 Typical Application of DP8409A Using External Control Access and Refresh in Modes 0 and 4
Resistors
DRAM load
DRAMs MAYBE 16K 64K OR 256K
FOR 4 BANKS CAN DRIVE 16 DATA BITS
FOR 2 BANKS CAN DRIVE 32 DATA BITS
FOR 1 BANK CAN DRIVE 64 DATA BITS
a
a
a
6 CHECK BITS FOR ECC
7 CHECK BITS FOR ECC
8 CHECK BITS FOR ECC
required
depends
on
9
(Continued)
operations However initialization sequence timing is under
system control which may provide some system advantage
MODE 4 EXTERNALLY CONTROLLED ACCESS
This mode facilitates externally controlling all access-timing
parameters associated with the DRAMs The application of
modes 0 and 4 are shown in Figure 6
Output Address Selection
Refer to Figure 7a With M2 (RFSH) and R C high the row
address latch contents are transferred to the multiplexed
address bus output Q0 – Q8 provided CS is set low The
column address latch contents are output after R C goes
low RASIN can go low after the row addresses have been
set up on Q0– Q8 This selects one of the RAS outputs
strobing the row address on the Q outputs into the desired
bank of memory After the row-address hold-time of the
DRAMs R C can go low so that about 40 ns later column
addresses appear on the Q outputs
TL F 8409 – 14