DP8409AN National Semiconductor, DP8409AN Datasheet - Page 6

• Manufacturer Part Number: DP8409AN
• Description: IC CONTROLLER DYNAMIC RAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8409AN

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 250mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8409AN

DP8409A Functional Mode Descriptions
MODE 1 AUTOMATIC FORCED REFRESH
In Mode 1 the R C (RFCK) pin becomes RFCK (refresh
cycle clock) instead of R C and CAS remains high If
RFCK is kept permanently high then whenever M2 (RFSH)
goes low an externally controlled refresh will occur and all
RAS outputs will follow RASIN strobing the refresh counter
contents to the DRAMs The RF I O pin will always output
high but when set low externally through an open-collector
driver the refresh counter resets as normal This externally
controlled method may be preferred when operating in the
Automatic Access mode (Mode 5) where hidden or forced
refreshing is undesirable but refreshing is still necessary
If RFCK is an input clock signal one (and only one) refresh
cycle must take place every RFCK cycle Refer to Figure 9
If a hidden refresh does not occur while RFCK is high in
Mode 5 then RF I O (Refresh Request) goes low immedi-
ately after RFCK goes low indicating to the system that a
forced refresh is requested The system must allow a forced
refresh to take place while RFCK is low (refer to Figure 3 )
The Refresh Request signal on RF I O may be connected
to a Hold or Bus Request input to the system The system
acknowledges the Hold or Bus Request when ready and
outputs Hold Acknowledge or Bus Request Acknowledge If
this is connected to the M2 (RFSH) pin a forced-refresh
cycle will be initiated by the DP8409A and RAS will be inter-
nally generated on all four RAS outputs to strobe the re-
fresh counter contents on the address outputs into all the
FIGURE 3 DP8409A Performing a Forced Refresh (Mode 5
6
(Continued)
DRAMs An external RAS Generator Clock (RGCK) is re-
quired for this function It is fed to the CASIN (RGCK) pin
and may be up to 10 MHz Whenever M2 goes low (inducing
a forced refresh) RAS remains high for one to two periods
of RGCK depending on when M2 goes low relative to the
high-to-low triggering edge of RGCK RAS then goes low for
two periods performing a refresh on all banks In order to
obtain the minimum delay from M2 going low to RAS going
low M2 should go low t
of RGCK The Refresh Request on RF I O is terminated as
RAS begins so that by the time the system has acknowl-
edged the removal of the request and disabled its Acknowl-
edge (i e M2 goes high) Refresh RAS will have ended
and normal operations can begin again in the Automatic
Access mode (Mode 5) If it is desired that Refresh RAS end
in less than 2 periods of RGCK from the time RAS went low
then M2 may be high earlier than t
low and RAS will go high t
is high the RAS will go high after 25 ns after M2 goes high
To allow the forced refresh the system will have been inac-
tive for about 4 periods of RGCK which can be as fast as
400 ns every RFCK cycle To guarantee a refresh of 128
rows every 2 ms a period of up to 16
RFCK In other words the system may be down for as little
as 400 ns every 16 s or 2 5% of the time Although this is
not excessive it may be preferable to perform a Hidden
Refresh each RFCK cycle which is allowed while still in the
Auto-Access mode (Mode 5)
1
5) with Various Microprocessors
RFSRG
RFRH
before the next falling edge
after M2 if CS is low If CS
RQHRF
after RGCK goes
s is required for
TL F 8409– 10