DP8409AN National Semiconductor, DP8409AN Datasheet - Page 7

• Manufacturer Part Number: DP8409AN
• Description: IC CONTROLLER DYNAMIC RAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8409AN

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 250mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8409AN

DP8409A Functional Mode Descriptions
MODE 2 AUTOMATIC BURST REFRESH
This mode is normally used before and or after a DMA op-
eration to ensure that all rows remain refreshed provided
the DMA transfer takes less than 2 ms (see Figure 4 ) When
the DP8409A enters this mode CASIN (RGCK) becomes
the RAS Generator Clock (RGCK) and RASIN is disabled
CAS remains high and RF I O goes low when the refresh
counter has reached the selected End-of-Count and the last
RAS has ended RF I O then remains low until the Auto-
Burst Refresh mode is terminated RF I O can therefore be
used as an interrupt to indicate the End-of-Burst conditions
The signal on all four RAS outputs is just a divide-by-four of
RGCK in other words if RGCK has a 100 ns period RAS is
high and low for 200 ns each cycle The refresh counter
increments at the end of each RAS starting from the count
it contained when the mode was entered If this was zero
then for a RGCK with a 100 ns period with End-of-Count set
to 127 RF I O will go low after 128
During this time the system may be performing operations
that do not involve DRAM If all rows need to be burst re-
freshed the refresh counter may be cleared by setting RF
I O low externally before the burst begins
Burst-mode refreshing is also useful when powering down
systems for long periods of time but with data retention still
required while the DRAMs are in standby To maintain valid
refreshing power can be applied to the DP8409A (set to
Mode 2) causing it to perform a complete burst refresh
When end-of-burst occurs (after 26 s) power can then be
removed from the DP8409A for 2 ms consuming an aver-
age power of 1 3% of normal operating power No control
signal glitches occur when switching power to the
DP8409A
MODE 3a ALL-RAS AUTOMATIC WRITE
Mode 3a is useful at system initialization when the memory
is being cleared (i e with all-zeros in the data field and the
c
0 4 s or 51 2 s
FIGURE 4 Auto-Burst Mode Mode 2
7
Figure 1b the 8 refresh counter bits are strobed by RAS into
5b ) A minimum of 30 ns after RAS goes low (t
(Continued)
corresponding check bits for error detection and correction)
This requires writing the same data to each location of
memory (every row of each column of each bank) All RAS
outputs are activated as in refresh and so are CAS and
WE To write to all four banks simultaneously every row is
strobed in each column in sequence until data has been
written to all locations
To select this mode B1 and B0 must have previously been
set to 00 01 or 10 in Mode 7 depending on the DRAM size
For example for 16k DRAMs B1 and B0 are 00 For 64k
DRAMs B1 and B0 are 01 so that for the configuration of
the 7 row addresses and the ninth column address After
this Automatic-Write process B1 and B0 must be set again
in Mode 7 to 00 to set End-of-Count to 127 For the configu-
ration of Figure 1c B1 and B0 set to 01 will work for Auto-
matic-Write and End-of-Count equals 255
In this mode R C is disabled WE is permanently enabled
low and CASIN (RGCK) becomes RGCK RF I O goes low
whenever the refresh counter is 127 255 or 511 (as set by
End-of-Count in Mode 7) and the RAS outputs are active
Referring to Figure 5a an external 8-bit counter (for 64k
DRAMs) with TRI-STATE outputs is required and must be
connected to the column address inputs It is enabled only
during this mode and is clocked from RF I O The
DP8409A refresh counter is used to address the rows and
the column address is supplied by the external counter Ev-
ery row for each column address is written to in all four
banks At the End-of-Count RF I O goes low which clocks
the external counter
Therefore for each column address the refresh counter
first outputs row-0 to the address bus and all four RAS out-
puts strobe this row address into the DRAMs (see Figure
30 ns) the refresh counter is disabled and the column ad-
TL F 8409 – 11
RAH
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