DP8409AN National Semiconductor, DP8409AN Datasheet - Page 19

• Manufacturer Part Number: DP8409AN
• Description: IC CONTROLLER DYNAMIC RAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8409AN

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 250mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8409AN

ACCESS (Continued)
t
t
t
t
t
t
t
t
t
t
t
REFRESH
t
t
t
t
t
t
t
t
t
t
t
t
t
t
T
t
t
t
Switching Characteristics DP8409A-2
V
of 22 DRAMs each or 88 DRAMs including trace capacitance These values are Q0– Q8 C
150 pF WE C
closed unless otherwise noted and R1 and R2 are 4 7 k
with all outputs switching
WPDL
WPDH
CRS
CPDL
CPDH
RCC
RCR
RHA
CCAS
DIF1
DIF2
RC
RASINL H
RFPDL
RFPDH
RFLCT
RFHRV
ROHNC
RLEOC
RHEOC
RGEOB
MCEOB
RST
CTL
RFCKL H
RGCKL
RGCKH
FRQL
Symbol
CC
e
5 0V
g
L
5% 0 C
WIN to WE Output Delay
WIN to WE Output Delay
CASIN Set-Up Time to RASIN High (Mode 6)
CASIN to CAS Delay (R C Low in Mode 4)
CASIN to CAS Delay (R C Low in Mode 4)
Column Select to Column Address Valid
Row Select to Row Address Valid
Row Address Held from Column Select
R C Low to CAS Low (Mode 4 Auto CAS)
Maximum (t
Maximum (t
Refresh Cycle Period
Pulse Width of RASIN during Refresh
RASIN to RAS Delay during Refresh
RASIN to RAS Delay during Refresh
RFSH Low to Counter Address Valid
RFSH High to Row Address Valid
RAS High to New Count Valid
RASIN Low to End-of-Count Low
RASIN High to End-of-Count High
RGCK Low to End-of-Burst Low
Mode Change to End-of-Burst High
Counter Reset Pulse Width
RF I O Low to Counter Outputs All Low
Minimum Pulse Width of RFCK
Period of RAS Generator Clock
Minimum Pulse Width Low of RGCK
Minimum Pulse Width High of RGCK
RFCK Low to Forced RFRQ Low
e
500 pF CAS C
s
T
RPDL
RCC
A s
b
Parameter
70 C (unless otherwise noted) (Notes 2 4 5) The output load capacitance is typical for 4 banks
b
t
CPDL
t
L
RHA
e
)
)
600 pF (unless otherwise noted) See Figure 11 for test load Switches S1 and S2 are
unless otherwise noted Maximum propagation delays are specified
19
(Continued)
Figure 7b
Figure 7b
Figure 8b
Figure 7b
Figure 7b
Figure 7a
Figures 7a 7b
Figure 7a
Figure 7a
Figure 2
Figure 2
Figures 2 9
Figures 2 9
Figures 2 3
Figures 2 4
Figure 2
Figure 2
Figure 9
Figure 3
Figure 3
Figure 3
See Mode 4 Descript
See Mode 4 Descript
CS
C
C
C
C
C
L
L
L
L
L
e
e
e
e
e
e
Conditions
50 pF Figure 2
50 pF Figure 2
50 pF Figure 4
50 pF Figure 4
50 pF Figure 3
X Figures 2 3 4
L
Min
100
100
100
15
15
35
32
25
10
50
35
30
70
35
35
e
500 pF RAS0– RAS3 C
8409A-2
Typ
25
30
41
39
40
40
55
50
40
47
45
30
20
Max
100
30
60
58
50
58
58
75
13
13
70
55
60
60
55
80
80
95
75
30
Units
L
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
e