DP8409AN National Semiconductor, DP8409AN Datasheet - Page 20

• Manufacturer Part Number: DP8409AN
• Description: IC CONTROLLER DYNAMIC RAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8409AN

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 250mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8409AN

Symbol
REFRESH (Continued)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Switching Characteristics DP8409A-2
V
of 22 DRAMs each or 88 DRAMs including trace capacitance These values are Q0 – Q8 C
150 pF WE C
closed unless otherwise noted and R1 and R2 are 4 7 k
with all outputs switching
Input Capacitance
Note 1 ‘‘Absolute Maximum Ratings’’ are the values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the device
should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation
Note 2 All typical values are for T
Note 3 This test is provided as a monitor of Driver output source and sink current capability Caution should be exercised in testing these parameters In testing
these parameters a 15
second
Note 4 Input pulse 0V to 3 0V t
for High and 0 8V for Low
Note 5 The load capacitance on RF I O should not exceed 50 pF
Note 6 Applies to all DP8409A versions unless otherwise specified
Note 7 The DP8409A-2 device can only be used with memory devices that meet the t
FRQH
RGRL
RGRH
RQHRF
RFRH
RFSRG
CSCT
CSRL
ZH
HZ
ZL
LZ
HZH
HHZ
HZL
LHZ
Symbol
C
C
CC
IN
IN
e
5 0V
g
RGCK Low to Forced RFRQ High
RGCK Low to RAS Low
RGCK Low to RAS High
RFSH Hold Time from RFSH RQST (RF I O)
RFSH High to RAS High (Ending Forced RFSH)
RFSH Low Set-Up to RGCK Low (Mode 1)
CS High to RFSH Counter Valid
CS Low to Access RASIN Low
CS Low to Address Output High from Hi-Z
CS High to Address Output Hi-Z from High
CS Low to Address Output Low from Hi-Z
CS High to Address Output Hi-Z from Low
CS Low to Control Output High from
Hi-Z High
CS High to Control Output Hi-Z High
from High
CS Low to Control Output Low from
Hi-Z High
CS High to Control Output Hi-Z High
from Low
L
5% 0 C
e
Input Capacitance ADS R C
Input Capacitance All Other Inputs
500 pF CAS C
resistor should be placed in series with each output under test One output should be tested at a time and test time should not exceed 1
s
R
T
e
A
A s
t
e
F
Parameter
e
T
Parameter
25 C and V
70 C (unless otherwise noted) (Notes 2 4 5) The output load capacitance is typical for 4 banks
A
2 5 ns f
e
L
25 C (Notes 2 6)
e
e
600 pF (unless otherwise noted) See Figure 11 for test load Switches S1 and S2 are
CC
2 5 MHz t
e
5 0V
PW
e
200 ns Input reference point on AC measurements is 1 5V Output reference points are 2 7V
unless otherwise noted Maximum propagation delays are specified
Conditions
20
(Continued)
Figure 3
Figure 3
Figure 3
Figure 9
Figures 9 12
Figures 9 12
Figures 9 12
Figures 9 12
Figures 9 12
Figures 9 12
Figure 12
Figure 12
C
See Mode 1 Descrip
See Mode 1 Descrip
See Mode 5 Descrip
R1
C
R2
R1
C
R1
R2
C
R2
S1 S2 Open
C
R2
L
L
L
L
L
e
e
e
e
e
RAH
e
e
e
e
e
e
e
Conditions
50 pF Figure 3
15 pF
15 pF
15 pF
15 pF
3 5k R2
1k S1 Open
3 5k R2
1k S2 Open
750
750
750
specification indicated
S1 Open
S1 Open
S1 Open
e
e
Min
1 5k
1 5k
L
Min
50
40
2T
55
35
30
Typ
e
8
5
500 pF RAS0– RAS3 C
8409A-2
Typ
50
65
60
80
55
35
20
35
25
50
40
45
50
Max
Max
110
75
95
85
70
60
40
60
50
80
75
75
80
Units
pF
pF
Units
L
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
e