DP8409AN National Semiconductor, DP8409AN Datasheet - Page 16

• Manufacturer Part Number: DP8409AN
• Description: IC CONTROLLER DYNAMIC RAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8409AN

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 250mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8409AN

ACCESS (Continued)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
REFRESH
t
t
t
t
t
CCDH
RAH
RAH
ASC
ASC
RCV
RCV
RPDL
RPDH
APDL
APDH
SPDL
SPDH
ASA
AHA
ADS
WPDL
WPDH
CRS
CPDL
CPDH
RCC
RCR
RHA
CCAS
DIF1
DIF2
RC
RASINL H
RFPDL
RFPDH
RFLCT
Symbol
Switching Characteristics DP8409A DP8409A-3
V
of 22 DRAMs each or 88 DRAMs including trace capacitance These values are Q0 – Q8 C
150 pF WE C
closed unless otherwise noted and R1 and R2 are 4 7 k
with all outputs switching
CC
e
5 0V
CASIN to CAS Output Delay (Mode 6)
Row Address Hold Time (Mode 5)
Row Address Hold Time (Mode 6)
Column Address Setup Time (Mode 5)
Column Address Setup Time (Mode 6)
RASIN to Column Address Valid (Mode 5)
RASIN to Column Address Valid (Mode 6)
RASIN to RAS Delay
RASIN to RAS Delay
Address Input to Output Low Delay
Address Input to Output High Delay
Address Strobe to Address Output Low
Address Strobe to Address Output High
Address Set-Up Time to ADS
Address Hold Time from ADS
Address Strobe Pulse Width
WIN to WE Output Delay
WIN to WE Output Delay
CASIN Set-Up Time to RASIN High (Mode 6) Figure 8b
CASIN to CAS Delay (R C Low in Mode 4)
CASIN to CAS Delay (R C Low in Mode 4)
Column Select to Column Address Valid
Row Select to Row Address Valid
Row Address Held from Column Select
R C Low to CAS Low (Mode 4 Auto CAS)
Maximum (t
Maximum (t
Refresh Cycle Period
Pulse Width of RASIN during Refresh
RASIN to RAS Delay during Refresh
RASIN to RAS Delay during Refresh
RFSH Low to Counter Address Valid
g
L
5% 0 C
e
500 pF CAS C
RPDL
RCC
s
T
b
Parameter
A s
b
t
CPDL
t
RHA
70 C (unless otherwise noted) (Notes 2 4 5) The output load capacitance is typical for 4 banks
L
)
)
e
600 pF (unless otherwise noted) See Figure 11 for test load Switches S1 and S2 are
Figure 8b
Figure 8a
Figures 8a 8b
Figure 8a
Figures 8a 8b
Figure 8a
Figures 8a 8b
Figures 7a 7b 8a 8b
Figures 7a 7b 8a 8b
Figures 7a 7b 8a 8b
Figures 7a 7b 8a 8b
Figures 7a 7b
Figures 7a 7b
Figures 7a 7b 8a 8b
Figures 7a 7b 8a 8b
Figures 7a 7b 8a 8b
Figure 7b
Figure 7b
Figure 7b
Figure 7b
Figure 7a
Figures 7a 7b
Figure 7a
Figure 7a
Figure 2
Figure 2
Figures 2 9
Figures 2 9
See Mode 4 Descrip
See Mode 4 Descrip
CS
unless otherwise noted Maximum propagation delays are specified
e
16
Conditions
X Figures 2 3 4
(Continued)
Min
100
40
30
20
20
15
15
15
30
15
15
35
32
25
10
50
35
30
8
6
DP8409A
Typ
54
90
75
27
23
25
25
40
40
25
30
41
39
40
40
65
50
40
47
L
e
Max
120
105
70
35
32
40
40
60
60
30
60
68
50
58
58
90
13
13
70
55
60
500 pF RAS0– RAS3 C
Min
100
40
30
20
20
15
15
15
30
15
15
35
32
25
10
50
35
30
8
6
DP8409A-3
Typ
54
90
75
27
23
25
25
40
40
25
30
41
39
40
40
50
40
47
Max
140
120
80
40
37
46
46
70
70
35
70
77
60
67
67
18
18
80
65
70
L
Units
e
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns