AD5933YRSZ Analog Devices Inc, AD5933YRSZ Datasheet - Page 13

• Manufacturer Part Number: AD5933YRSZ
• Description: IC NTWK ANALYZER 12B 1MSP 16SSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5933YRSZ

• Resolution (bits): 12 b
• Master Fclk: 16.776MHz
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP
• Supply Voltage Range: 2.7V To 5.5V
• Operating Temperature Range: -40°C To +125°C
• Digital Ic Case Style: SSOP
• No. Of Pins: 16
• Frequency Max: 0.1MHz
• Termination Type: SMD
• Pin Count: 16
• Screening Level: Automotive
• Package Type: SSOP
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Communication Function: Network Analyzer
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD5933EBZ - BOARD EVALUATION FOR AD5933
• Tuning Word Width (bits): -
• Lead Free Status / Rohs Status: Compliant
• Other names: AD5933BRSZ; Q2204656A

SYSTEM DESCRIPTION
The AD5933 is a high precision impedance converter system
solution that combines an on-board frequency generator with a
12-bit, 1 MSPS ADC. The frequency generator allows an external
complex impedance to be excited with a known frequency. The
response signal from the impedance is sampled by the on-board
ADC and DFT processed by an on-board DSP engine. The DFT
algorithm returns both a real (R) and imaginary (I) data-word at
each frequency point along the sweep. The impedance magnitude
and phase are easily calculated using the following equations:
To characterize an impedance profile Z( ω ), generally a frequency
sweep is required, like that shown in Figure 18.
Phase = tan
Magnitude
MICROCONTROLLER
Figure 18. Impedance vs. Frequency Profile
−1
=
( I / R )
R
2
+
SDA
SCL
I
2
FREQUENCY
REGISTER
OSCILLATOR
REAL
WINDOWING
INTERFACE
MAC CORE
(1024 DFT)
OF DATA
MCLK
I
2
C
IMAGINARY
REGISTER
(12 BITS)
MCLK
ADC
COS
Figure 17. Block Overview
Rev. C | Page 13 of 44
(27 BITS)
CORE
DDS
SIN
LPF
TEMPERATURE
AD5933
The AD5933 permits the user to perform a frequency sweep with
a user-defined start frequency, frequency resolution, and number
of points in the sweep. In addition, the device allows the user to
program the peak-to-peak value of the output sinusoidal signal as
an excitation to the external unknown impedance connected
between the VOUT and VIN pins.
Table 5 gives the four possible output peak-to-peak voltages and
the corresponding dc bias levels for each range for 3.3 V. These
values are ratiometric with VDD. So for a 5 V supply
Table 5. Voltage Levels Respective Bias Levels for 3.3 V
Range
1
2
3
4
The excitation signal for the transmit stage is provided on-chip
using DDS techniques that permit subhertz resolution. The receive
stage receives the input signal current from the unknown impedance,
performs signal processing, and digitizes the result. The clock for
the DDS is generated from either an external reference clock,
which is provided by the user at MCLK, or by the internal
oscillator. The clock for the DDS is determined by the status of
Bit D3 in the control register (see Register Address 0x81 in the
Register Map section).
Output
Output
SENSOR
PROGRAMMABLE
GAIN AMPLIFIER
Excitation
DC
DAC
Output Excitation
Voltage Amplitude
1.98 V p-p
0.97 V p-p
383 mV p-p
198 mV p-p
×5
×1
Bias
Voltage
Voltage
for
for
Range
Range
VDD/2
1
R
=
OUT
1
. 1
=
Output DC Bias Level
1.48 V
0.76 V
0.31 V
0.173 V
. 1
48
98
×
5
3
VOUT
RFB
VIN
×
0 .
3 .
Z(ω)
5
3
=
0 .
3 .
. 2
=
24
AD5933
3
V
V
p
p
−
−
p
p