CY7C924ADX-AXC Cypress Semiconductor Corp, CY7C924ADX-AXC Datasheet - Page 2

• Manufacturer Part Number: CY7C924ADX-AXC
• Description: IC TXRX HOTLINK 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink™r
• Type: Transceiverr

Specifications of CY7C924ADX-AXC

• Package / Case: 100-LQFP
• Protocol: Fibre Channel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 622 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current (max): 250 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage (typ): 5V
• Screening Level: Commercial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• No. Of Receivers: 2
• Frequency Max: 50MHz
• Rohs Compliant: Yes
• Termination Type: SMD
• Filter Terminals: SMD
• Driver Case Style: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 428-2918; CY7C924ADX-AXC

Document #: 38-02008 Rev. *E
CY7C924ADX Transceiver Logic Block Diagram
LOOPBACK
CONTROL
DLB[1:0]
LOOPTX
Flags
Transmit
Formatter
Output Register
STATUS
Pipeline Register
TX
8B/10B Encoder
Byte-Packer
3
BIST LFSR
Input Register
MUX
LOOPBACK
CONTROL
Transmit
MUX
FIFO
Serial Shifter
TXDATA
3
13
OUTA
CONTROL
CURSETA
Control
Mode
11
Bit Clock
MODE
9
TXCLK
OUTB
PLL Clock
Routing Matrix
Transmit
Multiplier
Elasticity
Transmit
Machine
Receive
Machine
Control
Control
Buffer
REFCLK
State
State
CURSETB
Flags
STATUS
Receive
Formatter
RX
INA
Address Matching
Output Register
Pipeline Register
8B/10B Decoder
Deserializer
Byte-Unpacker
Clock/Data
Receive
4
Recovery
Receive
FIFO
Framer
BIST LFSR
RXDATA
MUX
INB
13
MUX
Bit Clock
A/B*
Divider
Clock
Address Register
CY7C924ADX
Validation
CARDET
Signal
CONTROL
AM*
TXEN*
RXEN*
TXSTOP*
TXRST*
TXBISTEN*
MODE
RANGESEL
SPDSEL
RXMODE[1:0]
FIFOBYP*
EXTFIFO
ENCBYP*
BYTE8/10*
TEST*
RXSTATUS
LFI*
RXEMPTY*
RXHALF*
RXFULL*
RXRST*
RFEN
TX STATUS
TXEMPTY*
TXHALF*
TXFULL*
RXBISTEN*
RESET*[1:0]
Mode
Page 2 of 58
RXCLK
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