VSC8211XVW Vitesse Semiconductor Corp, VSC8211XVW Datasheet - Page 111

• Manufacturer Part Number: VSC8211XVW
• Description: IC PHY 10/100/1000 SGL 117-LBGA
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8211XVW

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 117-LBGA
• Case: BGA
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1023

1
2
25.3.25 Register 24 (18h) – PHY Control Register #2
24.15:13 – Reserved
These bits must always be written to as ‘111’.
24.12 - Enable PICMG Miser Mode
Setting bit 24.12 turns off some portions of the PHY's DSP block and reduces the PHY's Operating power. This bit can be set in
order to reduce power consumption in applications where the signal to noise ratio on the CAT-5 media is high, such as ethernet
over the backplane or where the cable length is short (<10m).
24.11:10 - Reserved
24.9:7 – TX FIFO Depth Control for RGMII, SGMII and Serial MAC
Bits 24.9:7 control symbol buffering for the transmit synchronization FIFO used in all 1000BT modes except for RTBI-Serdes/
Fiber mode. An internal FIFO is used to synchronize the clock domains between the MAC transmit clock and the PHY’s clock
(e.g., REFCLK), used to transmit symbols on the local PHY’s twisted pair interface.
The IEEE mode supports up to 1518-byte packet size with the minimum inter-packet gap (IPG). The jumbo packet mode adds
latency to the path to support up to 9600-byte packets with the minimum inter-packet gap (IPG). When using jumbo packet
mode, a larger IPG is recommended due to the possible compression of the IPG at the output of the FIFO.
1
2
VMDS-10105 Revision 4.1
October 2006
Bit
15:13 Reserved
12
11:10 Reserved
9:7
6:4
3:1
0
See
The TX and RX FIFOs are not used in MII mode for 10BASE-T and 100BASE-TX.
These bits must always be written to as ‘111’.
See
section 12, “Transformerless Operation for PICMG 2.16 and 3.0 IP-based Backplanes,”
section 12, “Transformerless Operation for PICMG 2.16 and 3.0 IP-based Backplanes,”
Register 24 (18h) – PHY Control Register #2
Name
Enable PICMG Miser Mode
TX FIFO Depth Control for RGMII,
SGMII and Serial MAC
RX FIFO Depth Control (RTBI only) R/W
Reserved
Connector Loopback
1
2
1
Access
RO
R/W
RO
R/W
RO
R/W
States
1 = PICMG Miser Mode Enabled
0 = PICMG Miser Mode Disabled
000 to 010 = Reserved
011 = Jumbo packet mode
100 = IEEE mode
101 to 111 = Reserved
000 to 010 = Reserved
011 = Jumbo packet mode
100 = IEEE mode
101 to 111 = Reserved
1 = Active (See
0 = Disable
111 of 165
Loopback"
2
for details)
Section 18.5: "Connector
page 45 for more information.
page 45 for more information.
Reset Value
111
0
00
100
100
000
0
Datasheet
VSC8211
Sticky
S
S
S
S