VSC8211XVW Vitesse Semiconductor Corp, VSC8211XVW Datasheet - Page 132

• Manufacturer Part Number: VSC8211XVW
• Description: IC PHY 10/100/1000 SGL 117-LBGA
• Manufacturer: Vitesse Semiconductor Corp
• Type: PHY Transceiverr

Specifications of VSC8211XVW

• Number Of Drivers/receivers: 1/1
• Protocol: Gigabit Ethernet
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 117-LBGA
• Case: BGA
• Dc: 07+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1023

29E.9:6 - Destination Address
The 6-byte destination address for packets generated by the EPG is assigned one of 16 values in the range 0xF0 FF FF FF FF
FFh through 0xFF FF FF FF FF FFh. The most significant byte’s lower nibble bits of the destination address are selected by bits
29E.9:6. If bits 29E.9:6 change during packet transmission, the new values will not take effect until the EPG Run/Stop bit
(29E.14) has been cleared and set to a “1” again.
29E.5:2 - Source Address
The 6-byte source address for packets generated by the EPG is assigned one of 16 values in the range 0xF0 FF FF FF FF FFh
through 0xFF FF FF FF FF FFh. The most significant byte’s lower nibble bits are selected by bits 29E.5:2. If bits 29E.5:2 change
during packet transmission, the new values will not take effect until the EPG Run/Stop bit (29E.14) has been cleared and set to
a “1” again.
29E.1 - TXER Control
When bit 29E.1 is set to a “1”, all packets generated by the EPG will have the TXER signal asserted. When this bit is cleared,
TXER is not asserted. If bit 29E.1 changes during packet transmission, the new value will not take effect until the EPG Run/Stop
bit (29E.14) has been cleared and set to a “1” again.
29E.0 - Bad FCS Generation
When bit 29E.0 is set to a “1”, the EPG will generate packets containing an invalid Frame Check Sequence (FCS). When this bit
is cleared, the all EPG packets will contain a valid Frame Check Sequence. If bit 29E.0 changes during packet transmission, the
new value will not take effect until the EPG Run/Stop bit (29E.14) has been cleared and set to a “1” again.
25.4.15 Register 30E (1Eh) - 1000BASE-T Packet Generator Register #2
30E.15:0 - EPG Packet Payload
Each packet generated by the EPG contains a repeating sequence of bits 30E.15:0 as the data payload. If bits 30E.15:0 change
during packet transmission, the new values will not take effect until the EPG Run/Stop bit (29E.14) has been cleared and set to
a “1” again.
1
VMDS-10105 Revision 4.1
October 2006
Bit
15:0 EPG Packet Payload
Refer to
Register 30E (1Eh) - 1000BASE-T Packet Generator Register #2
Name
section 18.1, “1000BASE-T Ethernet Packet Generator (EPG),”
Access
R/W
States
Data for packets generated by EPG
132 of 165
page 64 for more information.
1
Reset Value
00000000 00000000
Datasheet
VSC8211
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