PIC12F683-I/SN Microchip Technology Inc., PIC12F683-I/SN Datasheet - Page 11

• Manufacturer Part Number: PIC12F683-I/SN
• Description: 8 PIN, 3.5 KB FLASH, 128 RAM, 6 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F683-I/SN

• A/d Inputs: 4-Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 5
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin SOIC-N
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 3-1:
© 2006 Microchip Technology Inc.
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Legend:
Note 1:
Addr
INDF
TMR0
PCL
STATUS
FSR
GPIO
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
WDTCON
CMCON0
CMCON1
ADRESH
ADCON0
Name
—
—
—
—
—
—
—
—
—
—
– = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 18, 90
Timer0 Module Register
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Holding Register for the Least Significant Byte of the 16-bit TMR1
Holding Register for the Most Significant Byte of the 16-bit TMR1
Timer2 Module Register
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result
T1GINV
PIC12F683 SPECIAL REGISTERS SUMMARY BANK 0
ADFM
IRP
Bit 7
EEIF
GIE
—
—
—
—
—
—
—
(1)
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50, 90
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
RP1
COUT
VCFG
Bit 6
PEIE
ADIF
—
—
—
—
—
(1)
CCP1IF
DC1B1
Bit 5
T0IE
RP0
GP5
—
—
—
—
—
Write Buffer for upper 5 bits of Program Counter
WDTPS3
DC1B0
CINV
INTE
Bit 4
GP4
TO
—
—
—
WDTPS2 WDTPS1
CCP1M3
CHS1
GPIE
CMIF
Bit 3
GP3
CIS
PD
—
CCP1M2
OSFIF
CHS0
Bit 2
T0IF
CM2
GP2
—
Z
GO/DONE
WDTPS0
TMR1CS
CCP1M1
TMR2IF
T1GSS
Bit 1
INTF
CM1
GP1
DC
TMR1ON 0000 0000 47, 90
SWDTEN ---0 1000 97, 90
CMSYNC ---- --10 57, 90
CCP1M0 --00 0000 75, 90
PIC12F683
TMR1IF 000- 0000 16, 90
ADON
GPIF
Bit 0
CM0
GP0
C
xxxx xxxx 41, 90
0000 0000 18, 90
0001 1xxx 12, 90
xxxx xxxx 18, 90
--xx xxxx 31, 90
---0 0000 18, 90
0000 0000 14, 90
xxxx xxxx 44, 90
xxxx xxxx 44, 90
0000 0000 49, 90
xxxx xxxx 76, 90
xxxx xxxx 76, 90
-0-0 0000 56, 90
xxxx xxxx 61,90
00-- 0000 65,90
POR, BOR
Value on
DS41211C-page 9
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