PIC12F683-I/SN Microchip Technology Inc., PIC12F683-I/SN Datasheet - Page 58

• Manufacturer Part Number: PIC12F683-I/SN
• Description: 8 PIN, 3.5 KB FLASH, 128 RAM, 6 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F683-I/SN

• A/d Inputs: 4-Channel, 10-Bit
• Comparators: 1
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 5
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin SOIC-N
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC12F683
8.7
The comparator, if enabled before entering Sleep mode,
remains active during Sleep. The additional current
consumed by the comparator is shown separately in
Section 15.0 “Electrical Specifications”. If the
comparator is not used to wake the device, power
consumption can be minimized while in Sleep mode by
turning off the comparator. The comparator is turned off
by selecting mode CM<2:0> = 000 or CM<2:0> = 111
of the CMCON0 register.
A change to the comparator output can wake-up the
device from Sleep. To enable the comparator to wake
the device from Sleep, the CMIE bit of the PIE1 register
and the PEIE bit of the INTCON register must be set.
The instruction following the Sleep instruction always
executes following a wake from Sleep. If the GIE bit of
the INTCON register is also set, the device will then
execute the Interrupt Service Routine.
REGISTER 8-1:
DS41211C-page 56
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
U-0
—
Operation During Sleep
Unimplemented: Read as ‘0’
COUT: Comparator Output bit
When CINV = 0:
1 = V
0 = V
When CINV = 1:
1 = V
0 = V
Unimplemented: Read as ‘0’
CINV: Comparator Output Inversion bit
1 = Output inverted
0 = Output not inverted
CIS: Comparator Input Switch bit
When CM<2:0> = 110 or 101:
1 = CIN+ connects to V
0 = CIN- connects to V
When CM<2:0> = 0xx or 100 or 111:
CIS has no effect.
CM<2:0>: Comparator Mode bits (See Figure 8-5)
000 = CIN pins are configured as analog, COUT pin configured as I/O, Comparator output turned off
001 = CIN pins are configured as analog, COUT pin configured as Comparator output
010 = CIN pins are configured as analog, COUT pin configured as I/O, Comparator output available internally
011 = CIN- pin is configured as analog, CIN+ pin is configured as I/O, COUT pin configured as
100 = CIN- pin is configured as analog, CIN+ pin is configured as I/O, COUT pin is configured as I/O, Comparator output
101 = CIN pins are configured as analog and multiplexed, COUT pin is configured as
110 = CIN pins are configured as analog and multiplexed, COUT pin is configured as I/O,
111 = CIN pins are configured as I/O, COUT pin is configured as I/O, Comparator output disabled, Comparator off.
COUT
IN
IN
IN
IN
R-0
Comparator output, CV
available internally, CV
Comparator output, CV
Comparator output available internally, CV
+ > V
+ < V
+ < V
+ > V
CMCON0: COMPARATOR CONFIGURATION REGISTER
IN
IN
IN
IN
-
-
-
-
W = Writable bit
‘1’ = Bit is set
IN
IN
U-0
—
-
-
REF
REF
REF
is non-inverting input
is non-inverting input
is non-inverting input
R/W-0
CINV
REF
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
is non-inverting input
8.8
A device Reset forces the CMCON0 and CMCON1
registers to their Reset states. This forces the Compar-
ator module to be in the Comparator Reset mode
(CM<2:0> = 000). Thus, all comparator inputs are
analog inputs with the comparator disabled to consume
the smallest current possible.
R/W-0
CIS
Effects of a Reset
R/W-0
CM2
© 2006 Microchip Technology Inc.
x = Bit is unknown
R/W-0
CM1
R/W-0
CM0
bit 0