PIC16F870-I/SP Microchip Technology Inc., PIC16F870-I/SP Datasheet - Page 101

• Manufacturer Part Number: PIC16F870-I/SP
• Description: 28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F870-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 22
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

11.12 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscil-
lator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKI pin. That means that the WDT will run,
even if the clock on the OSC1/CLKI and OSC2/CLKO
pins of the device has been stopped, for example, by
execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up
(Watchdog Timer Wake-up). The TO bit in the STATUS
register will be cleared upon a Watchdog Timer
time-out.
The WDT can be permanently disabled by clearing
configuration bit WDTEN (Section 11.1).
FIGURE 11-10:
TABLE 11-7:
 2003 Microchip Technology Inc.
2007h
81h,181h
Legend:
Note 1:
Address
Note:
and
Shaded cells are not used by the Watchdog Timer.
See Register 11-1 for operation of these bits.
PSA and PS2:PS0 are bits in the OPTION_REG register.
Config. bits
OPTION_REG
continue
Name
SUMMARY OF WATCHDOG TIMER REGISTERS
WATCHDOG TIMER BLOCK DIAGRAM
WDT Timer
Enable Bit
WDT
with
RBPU
From TMR0 Clock Source
(Figure 5-1)
Bit 7
(1)
normal
BOREN
INTEDG
Bit 6
operation
0
1
(1)
PSA
M
U
X
T0CS
Bit 5
CP1
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
T0SE
Bit 4
CP0
0
Note 1: The CLRWDT and SLEEP instructions
Time-out
8 - to - 1 MUX
MUX
WDT
Postscaler
2: When a CLRWDT instruction is executed
PWRTEN
1
Bit 3
clear the WDT and the postscaler, if
assigned to the WDT, and prevent it from
timing out and generating a device
RESET condition.
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but
the prescaler assignment is not changed.
PSA
8
PIC16F870/871
(1)
PSA
To TMR0 (Figure 5-1)
WDTEN
Bit 2
PS2
PS2:PS0
FOSC1
Bit 1
PS1
DS30569B-page 99
FOSC0
Bit 0
PS0