PIC16F870-I/SP Microchip Technology Inc., PIC16F870-I/SP Datasheet - Page 84

• Manufacturer Part Number: PIC16F870-I/SP
• Description: 28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F870-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 22
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F870/871
10.1
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 10-2. The
source impedance (R
switch (R
required to charge the capacitor C
switch (R
(V
mended impedance for analog sources is 10 k . As
the impedance is decreased, the acquisition time may
EQUATION 10-1:
FIGURE 10-2:
DS30569B-page 82
T
T
T
DD
ACQ
C
ACQ
Note 1: The reference voltage (V
), see Figure 10-2. The maximum recom-
2: The charge holding capacitor (C
3: The maximum recommended impedance for analog sources is 10 k . This is required to meet the pin
4: After a conversion has completed, a 2.0 T
A/D Acquisition Requirements
SS
SS
=
=
=
=
=
=
=
=
) impedance varies over the device voltage
leakage specification.
During this time, the holding capacitor is not connected to the selected A/D input channel.
) impedance directly affect the time
Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
T
2 s + T
C
- 120 pF (1 k + 7 k + 10 k ) In(0.0004885)
16.47 s
2 s + 16.47 s + [(50°C – 25 C)(0.05 s/ C)
19.72 s
AMP
HOLD
Legend C
+ T
(R
C
VA
C
ACQUISITION TIME
+ [(Temperature – 25°C)(0.05 s/°C)]
ANALOG INPUT MODEL
IC
S
+ T
V
I
R
SS
C
) and the internal sampling
R
+ R
LEAKAGE
T
PIN
IC
HOLD
S
COFF
SS
ANx
+ R
C
5 pF
HOLD
PIN
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
HOLD
S
) In(1/2047)
various junctions
) must be allowed
REF
. The sampling
) has no effect on the equation, since it cancels itself out.
HOLD
V
DD
V
V
) is not discharged after each conversion.
T
T
= 0.6V
= 0.6V
AD
delay must complete before acquisition can begin again.
I
± 500 nA
LEAKAGE
be decreased. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
To
Equation 10-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, T
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
R
IC
calculate
1k
V
SS R
DD
Sampling
Switch
6V
5V
4V
3V
2V
SS
the
Sampling Switch
5 6 7 8 9 10 11
V
minimum
 2003 Microchip Technology Inc.
C
= DAC capacitance
= 120 pF
SS
(k )
HOLD
acquisition
ACQ
, see
time,