PIC16F870-I/SP Microchip Technology Inc., PIC16F870-I/SP Datasheet - Page 52
PIC16F870-I/SP
Manufacturer Part Number
PIC16F870-I/SP
Description
28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F870-ISP.pdf
(172 pages)
Specifications of PIC16F870-I/SP
A/d Inputs
5-Channel, 10-Bit
Cpu Speed
5 MIPS
Eeprom Memory
64 Bytes
Input Output
22
Interface
USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
PIC16F870-I/SP
Manufacturer:
MICROCHIP
Quantity:
5 600
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PIC16F870/871
6.1
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is F
(T1CON<2>), has no effect, since the internal clock is
always in sync.
FIGURE 6-1:
6.3
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI, when bit T1OSCEN is
set, or on pin RC0/T1OSO/T1CKI, when bit T1OSCEN
is cleared.
FIGURE 6-2:
DS30569B-page 50
T1CKI
(Default High)
T1CKI
(Default Low)
Note: Arrows indicate counter increments.
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
RC0/T1OSO/T1CKI
Timer1 Operation in Timer Mode
Timer1 Operation in Synchronized
Counter Mode
OSC
/4. The synchronize control bit, T1SYNC
RC1/T1OSI
Set Flag bit
TMR1IF on
Overflow
TIMER1 INCREMENTING EDGE
TIMER1 BLOCK DIAGRAM
TMR1H
T1OSC
TMR1
TMR1L
Oscillator
T1OSCEN
Enable
(1)
Clock
F
Internal
OSC
/4
TMR1ON
6.2
Timer1 may operate in either a Synchronous, or an
Asynchronous mode, depending on the setting of the
TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut-off. The
prescaler, however, will continue to increment.
On/Off
TMR1CS
1
0
Timer1 Counter Operation
T1CKPS1:T1CKPS0
T1SYNC
Prescaler
1, 2, 4, 8
0
1
2
2003 Microchip Technology Inc.
Synchronized
Clock Input
Synchronize
Q Clock
det
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