PIC16F870-I/SP Microchip Technology Inc., PIC16F870-I/SP Datasheet - Page 79

• Manufacturer Part Number: PIC16F870-I/SP
• Description: 28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F870-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 22
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

9.4.2
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode. Bit SREN is a “don't care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
TABLE 9-11:
 2003 Microchip Technology Inc.
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
1Ah
8Ch
98h
99h
Legend:
Note 1:
Address
x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave reception.
Bits PSPIE and PSPIF are reserved on the PIC16F870, always maintain these bits clear.
USART SYNCHRONOUS SLAVE
RECEPTION
INTCON
PIR1
RCSTA
RCREG
PIE1
TXSTA
SPBRG
Name
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
USART Receive Register
Baud Rate Generator Register
PSPIF
PSPIE
CSRC
SPEN
Bit 7
GIE
(1)
(1)
ADIE
PEIE
ADIF
Bit 6
RX9
TX9
SREN
TXEN
RCIF
RCIE
Bit 5
T0IE
CREN ADDEN
SYNC
INTE
TXIE
Bit 4
TXIF
RBIE
Bit 3
—
—
—
When setting up a Synchronous Slave Reception,
follow these steps:
1.
2.
3.
4.
5.
6.
7.
8.
9.
CCP1IF
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
BRGH
FERR
Bit 2
T0IF
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TMR2IF TMR1IF 0000 -000 0000 -000
OERR
TRMT
Bit 1
INTF
PIC16F870/871
RX9D
TX9D
Bit 0
R0IF
0000 000x 0000 000x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
0000 000x
POR, BOR
Value on:
DS30569B-page 77
0000 000u
Value on
RESETS
all other