PIC16F870-I/SP Microchip Technology Inc., PIC16F870-I/SP Datasheet - Page 16

• Manufacturer Part Number: PIC16F870-I/SP
• Description: 28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F870-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 22
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F870/871
TABLE 2-1:
DS30569B-page 14
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note 1:
Address
Bank 1
(4)
(4)
(4)
(4)
(5)
(5)
(1,4)
(4)
2:
3:
4:
5:
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
PR2
TXSTA
SPBRG
ADRESL
ADCON1
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
Name
—
—
—
—
—
—
—
—
—
—
—
—
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter's (PC) Least Significant Byte
Indirect Data Memory Address Pointer
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
Unimplemented
Unimplemented
Unimplemented
Timer2 Period Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Baud Rate Generator Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
A/D Result Register Low Byte
PSPIE
RBPU
CSRC
ADFM
Bit 7
GIE
IRP
IBF
—
—
—
—
(3)
INTEDG
Bit 6
PEIE
ADIE
OBF
RP1
TX9
—
—
—
—
—
PORTA Data Direction Register
TXEN
Bit 5
T0CS
IBOV
RCIE
T0IE
RP0
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
PSPMODE
SYNC
Bit 4
T0SE
INTE
EEIE
TXIE
TO
—
—
PCFG3
Bit 3
RBIE
PSA
PD
—
—
—
—
—
PORTE Data Direction Bits
CCP1IE
PCFG2
BRGH
Bit 2
T0IF
PS2
—
—
Z
TMR2IE
PCFG1
TRMT
Bit 1
INTF
POR
PS1
DC
—
 2003 Microchip Technology Inc.
TMR1IE
PCFG0
TX9D
Bit 0
RBIF
BOR
PS0
—
C
POR, BOR
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
0000 -111 0000 -111
---0 0000 ---0 0000
0000 000x 0000 000u
0000 -000 0000 -000
---0 ---- ---0 ----
---- --qq ---- --uu
1111 1111 1111 1111
0000 -010 0000 -010
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0--- 0000
Value on:
—
—
—
—
—
—
—
—
—
—
—
—
RESETS
0--- 0000
Value on
all other
—
—
—
—
—
—
—
—
—
—
—
—
(2)