PIC18F2431-I/SP Microchip Technology Inc., PIC18F2431-I/SP Datasheet - Page 153

• Manufacturer Part Number: PIC18F2431-I/SP
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2431-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

15.0
The CCP (Capture/Compare/PWM) module contains a
16-bit register that can operate as a 16-bit Capture reg-
ister, a 16-bit Compare register or a PWM Master/Slave
Duty Cycle register. Table 15-1 shows the timer
resources required for each of the CCP module modes.
The operation of CCP1 is identical to that of CCP2, with
the exception of the special event trigger. Therefore,
operation of a CCP module is described with respect to
CCP1, except where noted.
REGISTER 15-1:
 2003 Microchip Technology Inc.
CAPTURE/COMPARE/PWM
(CCP) MODULES
bit 7-6
bit 5-4
bit 3-0
CCPxCON: CCP MODULE CONTROL REGISTER
bit 7
Unimplemented: Read as ‘0’
DCxB1:DCxB0: PWM Duty Cycle bit1 and bit0
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The upper eight bits
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
CCPxM3:CCPxM0: CCPx Mode Select bits
0000 =Capture/Compare/PWM disabled (resets CCPx module)
0001 =Reserved
0010 =Compare mode, toggle output on match (CCPxIF bit is set)
0011 =Reserved
0100 =Capture mode, every falling edge
0101 =Capture mode, every rising edge
0110 =Capture mode, every 4th rising edge
0111 =Capture mode, every 16th rising edge
1000 =Compare mode, Initialize CCP pin Low, on compare match force CCP pin High
1001 =Compare mode, Initialize CCP pin High, on compare match force CCP pin Low
1010 =Compare mode, Generate software interrupt-on-compare match (CCPxIF bit is set,
1011 =Compare mode, Trigger special event (CCP2IF bit is set)
11xx =PWM mode
Legend:
R = Readable bit
- n = Value at POR
U-0
—
(CCPxIF bit is set)
(CCPxIF bit is set)
CCP pin is unaffected)
U-0
—
PIC18F2331/2431/4331/4431
DCxB1
R/W-0
Preliminary
W = Writable bit
‘1’ = Bit is set
DCxB0
R/W-0
CCPxM3
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
CCPxM2
R/W-0
x = Bit is unknown
CCPxM1
R/W-0
DS39616B-page 151
CCPxM0
R/W-0
bit 0