PIC18F2431-I/SP Microchip Technology Inc., PIC18F2431-I/SP Datasheet - Page 330

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PIC18F2431-I/SP

Manufacturer Part Number
PIC18F2431-I/SP
Description
Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F2431-I/SP

A/d Inputs
5-Channel, 10-Bit
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
24
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2431-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
PIC18F2431-I/SP
Quantity:
5
PIC18F2331/2431/4331/4431
TSTFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39616B-page 328
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC = Address (HERE)
If CNT
PC
If CNT
PC
No
No
No
Q1
Q1
Q1
register ‘f’
operation
operation
operation
Test f, skip if 0
[ label ] TSTFSZ f [,a]
0
a
skip if f = 0
None
If ‘f’ = 0, the next instruction,
fetched during the current instruc-
tion execution, is discarded and a
NOP is executed, making this a two-
cycle instruction. If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ is 1,
then the bank will be selected as
per the BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0110
No
No
No
Q2
Q2
Q2
=
=
=
f
[0,1]
by a 2-word instruction.
255
0x00,
Address (ZERO)
0x00,
Address (NZERO)
:
TSTFSZ
011a
:
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
CNT
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
Preliminary
XORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
=
=
literal ‘k’
(W) .XOR. k
N, Z
Exclusive OR literal with W
[ label ] XORLW k
0
The contents of W are XORed
with the 8-bit literal ‘k’. The result
is placed in W.
1
1
XORLW 0xAF
Read
Q2
0000
0xB5
0x1A
 2003 Microchip Technology Inc.
k
255
1010
Process
Data
Q3
W
kkkk
Write to W
Q4
kkkk

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