PIC18F2431-I/SP Microchip Technology Inc., PIC18F2431-I/SP Datasheet - Page 280

• Manufacturer Part Number: PIC18F2431-I/SP
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2431-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2331/2431/4331/4431
22.2
For PIC18F2331/2431/4331/4431 devices, the WDT is
driven by the INTRC source. When the WDT is
enabled, the clock source is also enabled. The nominal
WDT period is 4 ms and has the same stability as the
INTRC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in
Configuration
Available periods range from 4 ms to 131.072 seconds
(2.18 minutes). The WDT and postscaler are cleared
when any of the following events occur: execute a
SLEEP
(OSCCON<6:4>) are changed, or a clock failure has
occurred (see Section 22.4.1 “FSCM and the
Watchdog Timer”).
Adjustments to the internal oscillator clock period using
the OSCTUNE register also affect the period of the
WDT by the same factor. For example, if the INTRC
period is increased by 3%, then the WDT period is
increased by 3%.
FIGURE 22-1:
REGISTER 22-15: WDTCON REGISTER
DS39616B-page 278
Change on IRCF Bits
All Device Resets
INTRC Source
WDTPS<3:0>
Watchdog Timer (WDT)
or
SWDTEN
CLRWDT
CLRWDT
WDTEN
bit 7
bit 6
bit 0
Register
Sleep
WDT BLOCK DIAGRAM
bit 7
WDTW: Watchdog Timer Window bit
1 = WDT count is in fourth quadrant
0 = WDT count is not in fourth quadrant
Unimplemented
SWDTEN: Software Enable / Disable for Watch Dog Timer bit
1 = WDT is turned on
0 = WDT is turned off
Legend:
R = Readable bit
U = Unimplemented bit, read as ‘0’
instruction,
WDTW
Note 1: If WDTEN configuration bit = 1, then WDT is always enabled, irrespective of this control
R-0
2H
Enable WDT
(see
bit. If WDTEN configuration bit = 0, then it is possible to turn WDT on/off with this con-
trol bit.
the
U-0
WDT Counter
—
Register 22-3).
IRCF
125
INTRC Control
4
U-0
—
Preliminary
bits
Programmable Postscaler
1:1 to 1:32,768
U-0
—
22.2.1
Register 22-15 shows the WDTCON register. This is a
readable and writable register. The SWDTEN bit allows
software to enable or disable the WDT, but only if the
configuration bit has disabled the WDT. The WDTW bit
is a read-only bit that indicates when the WDT count is
in the fourth quadrant (i.e., when the 8-bit WDT value is
b’11000000’ or greater).
W = Writable bit
- n = Value at POR
Note 1: The CLRWDT and SLEEP instructions
2: Changing the setting of the IRCF bits
3: When a CLRWDT instruction is executed
4: If WINEN = 0, then CLRWDT must be
WDT
U-0
—
CONTROL REGISTER
clear the WDT and postscaler counts
when executed.
(OSCCON<6:4> clears the WDT and
postscaler counts.
the postscaler count will be cleared.
executed only when WDTW = 1; other-
wise, a device reset will result.
Reset
(1)
U-0
—
 2003 Microchip Technology Inc.
U-0
—
WDT
Reset
Wake-up
from Sleep
SWDTEN
R/W-0
bit 0