PIC18F2431-I/SP Microchip Technology Inc., PIC18F2431-I/SP Datasheet - Page 223

• Manufacturer Part Number: PIC18F2431-I/SP
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2431-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

19.0
The Universal Synchronous Asynchronous Receiver
Transmitter (EUSART) module is one of the two serial
I/O modules available in the PIC18F2331/2431/4331/
4431 family of microcontrollers. EUSART is also known
as a Serial Communications Interface or SCI.
The EUSART can be configured as a full-duplex
asynchronous system that can communicate with
peripheral devices, such as CRT terminals and
personal computers. It can also be configured as a half-
duplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
The EUSART module implements additional features,
including
calibration, automatic wake-up on sync break reception
and 12-bit break character transmit. These make it
ideally suited for use in Local Interconnect Network
(LIN) bus systems.
The USART can be configured in the following modes:
• Asynchronous (full-duplex) with:
• Synchronous – Master (half-duplex) with
• Synchronous – Slave (half-duplex) with selectable
In order to configure pins RC6/TX/CK/SS and RC7/RX/
DT/SDO as the Universal Synchronous Asynchronous
Receiver Transmitter:
• SPEN (RCSTA<7>) bit must be set ( = 1),
• TRISC<6> bit must be set ( = 1), and
• TRISC<1> bit must be set ( = 1).
The operation of the enhanced USART module is
controlled through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCTL)
These are detailed in on the following pages in
Register 19-1,
respectively.
 2003 Microchip Technology Inc.
- Auto-Wake-up on character reception
- Auto-Baud calibration
- 12-bit break character transmission
selectable clock polarity
clock polarity
Note:
ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
automatic
The USART control will automatically
reconfigure the pin from input to output as
needed.
Register 19-2
baud
rate
and
detection
Register 19-3,
PIC18F2331/2431/4331/4431
and
Preliminary
19.1
The USART may operate in Asynchronous mode, while
the peripheral clocks are being provided by the internal
oscillator block. This makes it possible to remove the
crystal or resonator that is commonly connected as the
primary clock on the OSC1 and OSC2 pins.
The factory calibrates the internal oscillator block out-
put (INTOSC) for 8 MHz (see Table 25-6). However,
this frequency may drift as V
changes, and this directly affects the asynchronous
baud rate. Two methods may be used to adjust the
baud rate clock, but both require a reference clock
source of some kind.
The first (preferred) method uses the OSCTUNE
register to adjust the INTOSC output back to 8 MHz.
Adjusting the value in the OSCTUNE register allows for
fine resolution changes to the system clock source (see
Section 3.6 “INTOSC Frequency Drift” for more
information).
The other method adjusts the value in the baud rate
generator. There may not be fine enough resolution
when adjusting the Baud Rate Generator to compen-
sate for a gradual change in the peripheral clock
frequency.
Asynchronous Operation in
Power-Managed Modes
DD
DS39616B-page 221
or temperature